blob: 770df4dd98c578449b78e23e7a4d1ae662b05111 [file] [log] [blame]
Stefan Reinauer3e03d032006-09-08 16:34:51 +00001- 2.0.0
2 - this NEWS file is neglected in favor of the svn commit logs.
Stefan Reinauerf8ee1802008-01-18 15:08:58 +00003 See
arch import user (historical)3f8eb7a2005-07-06 16:48:00 +00004- 1.1.8
5 - Store everything in arch
Eric Biedermandbec2d42004-10-21 10:44:08 +00006- 1.1.7
7 - The configuration language has been cleaned up. No more link keyword.
8 - Everything is now in the device tree.
9 - The static and dynamic device trees have been unified
10 - Support for setting the pci subsystem vendor and pci subsystem device has been added.
11 - 64bit resource support
12 - Generic smbus support
Eric Biederman5cd81732004-03-11 15:01:31 +000013- 1.1.6
14 - pnp/superio devices are now handled cleanly with very little code
15 - Initial support for finding x86 BIST errors
16 - static resource assignments can now be specified in
17 - special VGA I/O decode now should work
18 - added generic PCI error reporting enables
19 - build_opt_tbl now generates a header that allows cmos settings to
20 be read from romcc compiled code.
22 - romcc now gracesfully handles function pointers instead of dying mysteriously
23 - First regression test in amdk8/raminit_test
Eric Biederman83b991a2003-10-11 06:20:25 +000024- 1.1.5
25 - O2, enums, and switch statements work in romcc
26 - Support for compiling romcc on non x86 platforms
27 - new romc options -msse and -mmmx for specifying extra registers to use
28 - Bug fixes to device the device disable/enable framework and an amd8111 implementation
29 - Move the link specification to the chip specification instead of the path
30 - Allow specifying devices with internal bridges.
31 - Initial via epia support
32 - Opteron errata fixes
Eric Biederman0ac6b412003-09-02 17:16:48 +000033- 1.1.4
34 Major restructuring of hypertransport handling.
35 Major rewerite of superio/NSC/pc87360 as a proof of concept for handling superio resources dynamically
36 Updates to hard_reset handling when resetting because of the need to change hypertransport link
37 speeds and widths.
38 (a) No longer assume the boot is good just because we get to a hard reset point.
39 (b) Set a flag to indicate that the BIOS triggered the reset so we don't decrement the
40 boot counter.
41 Updates to arima/hdama mptable so it tracks the new bus numbers
Eric Biedermane9a271e32003-09-02 03:36:25 +000042- 1.1.3
43 Major update of the dyanmic device tree to so it can handle
44 * subtractive resources
45 * merging with the static device tree
46 * more device types than just pci
Eric Biederman30e143a2003-09-01 23:45:32 +000047- 1.1.2
48 Add back in the hard_reset method from freebios1 this allows generic
Eric Biedermand4c14522003-09-01 23:47:37 +000049 code to reset the box.
50 Update the hypertransport setup code to automatically optimize
51 hypertransport link widths and frequencies, and to call hard_reset
52 if necessary for the changes to go into effect.
Eric Biederman9bdb4602003-09-01 23:17:58 +000053- 1.1.1
54 Updates to the new configuration system so it works more reliably
55 Removed a bunch of unused configuration variables
56 Removed a bunch of unused assembly code
57- 1.1.0
58 A whole bunch of random ppc and opteron work we never put a good label on
Eric Biederman77d1a832003-04-15 00:44:05 +000059- 1.1.0
60Intial development release of LinuxBIOS.
61Everything is thrown overboard and will be reincluded as necessary so we can
62get rid of the legacy baggage. Since LinuxBIOS was started we have developed
63some better techniques for some things, but we still hang on to the old ways
64because some ports that we want not to break depend on them. So we preserve
65them by preserve the 1.0.x series and keeping only the best practices for
66the 1.1.x series. When there is a stable port this code base will
67become LinuxBIOS 2.0.x and the core will become frozen.