Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | //#define SYSTEM_TYPE 0 /* SERVER */ |
| 21 | #define SYSTEM_TYPE 1 /* DESKTOP */ |
| 22 | //#define SYSTEM_TYPE 2 /* MOBILE */ |
| 23 | |
| 24 | //used by incoherent_ht |
| 25 | #define FAM10_SCAN_PCI_BUS 0 |
| 26 | #define FAM10_ALLOCATE_IO_RANGE 0 |
| 27 | |
| 28 | #include <stdint.h> |
| 29 | #include <string.h> |
| 30 | #include <device/pci_def.h> |
| 31 | #include <device/pci_ids.h> |
| 32 | #include <arch/io.h> |
| 33 | #include <device/pnp_def.h> |
| 34 | #include <arch/romcc_io.h> |
| 35 | #include <cpu/x86/lapic.h> |
| 36 | #include <console/console.h> |
| 37 | #include <cpu/amd/model_10xxx_rev.h> |
| 38 | #include "northbridge/amd/amdfam10/raminit.h" |
| 39 | #include "northbridge/amd/amdfam10/amdfam10.h" |
| 40 | #include <lib.h> |
| 41 | #include "cpu/x86/lapic/boot_cpu.c" |
| 42 | #include "northbridge/amd/amdfam10/reset_test.c" |
| 43 | #include <console/loglevel.h> |
| 44 | #include "cpu/x86/bist.h" |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 45 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 46 | #include <cpu/amd/mtrr.h> |
| 47 | #include "northbridge/amd/amdfam10/setup_resource_map.c" |
| 48 | #include "southbridge/amd/rs780/early_setup.c" |
| 49 | #include "southbridge/amd/sb800/early_setup.c" |
| 50 | #include "northbridge/amd/amdfam10/debug.c" |
Patrick Georgi | c9a08dd | 2011-03-04 17:09:21 +0000 | [diff] [blame] | 51 | #include <spd.h> |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 52 | |
| 53 | static void activate_spd_rom(const struct mem_controller *ctrl) |
| 54 | { |
| 55 | } |
| 56 | |
| 57 | static int spd_read_byte(u32 device, u32 address) |
| 58 | { |
| 59 | return smbus_read_byte(device, address); |
| 60 | } |
| 61 | |
| 62 | #include "northbridge/amd/amdfam10/amdfam10.h" |
| 63 | #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" |
| 64 | #include "northbridge/amd/amdfam10/pci.c" |
| 65 | #include "resourcemap.c" |
| 66 | #include "cpu/amd/quadcore/quadcore.c" |
| 67 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 68 | #include "cpu/amd/microcode/microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 69 | |
| 70 | #if CONFIG_UPDATE_CPU_MICROCODE |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 71 | #include "cpu/amd/model_10xxx/update_microcode.c" |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 72 | #endif |
| 73 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 74 | #include "cpu/amd/model_10xxx/init_cpus.c" |
| 75 | #include "northbridge/amd/amdfam10/early_ht.c" |
| 76 | |
| 77 | #define RC00 0 |
| 78 | #define RC01 1 |
| 79 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 80 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
| 81 | { |
| 82 | struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
| 83 | static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; |
| 84 | u32 bsp_apicid = 0, val; |
| 85 | msr_t msr; |
| 86 | |
| 87 | if (!cpu_init_detectedx && boot_cpu()) { |
| 88 | /* Nothing special needs to be done to find bus 0 */ |
| 89 | /* Allow the HT devices to be found */ |
| 90 | /* mov bsp to bus 0xff when > 8 nodes */ |
| 91 | set_bsp_node_CHtExtNodeCfgEn(); |
| 92 | enumerate_ht_chain(); |
| 93 | |
| 94 | /* enable port80 decoding and southbridge poweron init */ |
| 95 | sb800_lpc_port80(); |
| 96 | inb(0x80); /* Wait sometime before post to port80, otherwise reset was needed. */ |
| 97 | } |
| 98 | |
| 99 | post_code(0x30); |
| 100 | |
| 101 | if (bist == 0) { |
| 102 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ |
| 103 | /* All cores run this but the BSP(node0,core0) is the only core that returns. */ |
| 104 | } |
| 105 | |
| 106 | post_code(0x32); |
| 107 | |
| 108 | enable_rs780_dev8(); |
| 109 | sb800_lpc_init(); |
| 110 | |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 111 | console_init(); |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 112 | |
| 113 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
| 114 | |
| 115 | /* Halt if there was a built in self test failure */ |
| 116 | report_bist_failure(bist); |
| 117 | |
| 118 | // Load MPB |
| 119 | val = cpuid_eax(1); |
| 120 | printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); |
| 121 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
| 122 | printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); |
| 123 | printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); |
| 124 | |
| 125 | /* Setup sysinfo defaults */ |
| 126 | set_sysinfo_in_ram(0); |
| 127 | |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 128 | #if CONFIG_UPDATE_CPU_MICROCODE |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 129 | update_microcode(val); |
Xavi Drudis Ferran | 4c28a6f | 2011-02-26 23:29:44 +0000 | [diff] [blame] | 130 | #endif |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 131 | post_code(0x33); |
| 132 | |
| 133 | cpuSetAMDMSR(); |
| 134 | post_code(0x34); |
| 135 | |
| 136 | amd_ht_init(sysinfo); |
| 137 | post_code(0x35); |
| 138 | |
| 139 | /* Setup nodes PCI space and start core 0 AP init. */ |
| 140 | finalize_node_setup(sysinfo); |
| 141 | |
| 142 | /* Setup any mainboard PCI settings etc. */ |
| 143 | setup_mb_resource_map(); |
| 144 | post_code(0x36); |
| 145 | |
| 146 | /* wait for all the APs core0 started by finalize_node_setup. */ |
| 147 | /* FIXME: A bunch of cores are going to start output to serial at once. |
| 148 | It would be nice to fixup prink spinlocks for ROM XIP mode. |
| 149 | I think it could be done by putting the spinlock flag in the cache |
| 150 | of the BSP located right after sysinfo. |
| 151 | */ |
| 152 | wait_all_core0_started(); |
| 153 | |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame^] | 154 | #if CONFIG_LOGICAL_CPUS |
Zheng Bao | 8210e89 | 2011-01-20 05:29:37 +0000 | [diff] [blame] | 155 | /* Core0 on each node is configured. Now setup any additional cores. */ |
| 156 | printk(BIOS_DEBUG, "start_other_cores()\n"); |
| 157 | start_other_cores(); |
| 158 | post_code(0x37); |
| 159 | wait_all_other_cores_started(bsp_apicid); |
| 160 | #endif |
| 161 | |
| 162 | post_code(0x38); |
| 163 | |
| 164 | /* run _early_setup before soft-reset. */ |
| 165 | rs780_early_setup(); |
| 166 | sb800_early_setup(); |
| 167 | |
| 168 | #if CONFIG_SET_FIDVID |
| 169 | msr = rdmsr(0xc0010071); |
| 170 | printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
| 171 | |
| 172 | /* FIXME: The sb fid change may survive the warm reset and only |
| 173 | need to be done once.*/ |
| 174 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 175 | |
| 176 | post_code(0x39); |
| 177 | |
| 178 | if (!warm_reset_detect(0)) { // BSP is node 0 |
| 179 | init_fidvid_bsp(bsp_apicid, sysinfo->nodes); |
| 180 | } else { |
| 181 | init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 |
| 182 | } |
| 183 | |
| 184 | post_code(0x3A); |
| 185 | |
| 186 | /* show final fid and vid */ |
| 187 | msr=rdmsr(0xc0010071); |
| 188 | printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); |
| 189 | #endif |
| 190 | |
| 191 | rs780_htinit(); |
| 192 | |
| 193 | /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ |
| 194 | if (!warm_reset_detect(0)) { |
| 195 | print_info("...WARM RESET...\n\n\n"); |
| 196 | soft_reset(); |
| 197 | die("After soft_reset_x - shouldn't see this message!!!\n"); |
| 198 | } |
| 199 | |
| 200 | post_code(0x3B); |
| 201 | |
| 202 | /* It's the time to set ctrl in sysinfo now; */ |
| 203 | printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); |
| 204 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
| 205 | |
| 206 | post_code(0x40); |
| 207 | |
| 208 | // die("Die Before MCT init."); |
| 209 | |
| 210 | printk(BIOS_DEBUG, "raminit_amdmct()\n"); |
| 211 | raminit_amdmct(sysinfo); |
| 212 | post_code(0x41); |
| 213 | |
| 214 | /* |
| 215 | dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); |
| 216 | dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); |
| 217 | dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); |
| 218 | dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); |
| 219 | */ |
| 220 | |
| 221 | // ram_check(0x00200000, 0x00200000 + (640 * 1024)); |
| 222 | // ram_check(0x40200000, 0x40200000 + (640 * 1024)); |
| 223 | |
| 224 | // die("After MCT init before CAR disabled."); |
| 225 | |
| 226 | rs780_before_pci_init(); |
| 227 | sb800_before_pci_init(); |
| 228 | |
| 229 | post_code(0x42); |
| 230 | post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. |
| 231 | post_code(0x43); // Should never see this post code. |
| 232 | } |
Scott Duplichan | 314dd0b | 2011-03-08 23:01:46 +0000 | [diff] [blame] | 233 | |
| 234 | /** |
| 235 | * BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, u8 **List) |
| 236 | * Description: |
| 237 | * This routine is called every time a non-coherent chain is processed. |
| 238 | * BUID assignment may be controlled explicitly on a non-coherent chain. Provide a |
| 239 | * swap list. The first part of the list controls the BUID assignment and the |
| 240 | * second part of the list provides the device to device linking. Device orientation |
| 241 | * can be detected automatically, or explicitly. See documentation for more details. |
| 242 | * |
| 243 | * Automatic non-coherent init assigns BUIDs starting at 1 and incrementing sequentially |
| 244 | * based on each device's unit count. |
| 245 | * |
| 246 | * Parameters: |
| 247 | * @param[in] u8 node = The node on which this chain is located |
| 248 | * @param[in] u8 link = The link on the host for this chain |
| 249 | * @param[out] u8** list = supply a pointer to a list |
| 250 | * @param[out] BOOL result = true to use a manual list |
| 251 | * false to initialize the link automatically |
| 252 | */ |
| 253 | BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) |
| 254 | { |
| 255 | static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; |
| 256 | /* If the BUID was adjusted in early_ht we need to do the manual override */ |
| 257 | if ((node == 0) && (link == 0)) { /* BSP SB link */ |
| 258 | *List = swaplist; |
| 259 | return 1; |
| 260 | } |
| 261 | |
| 262 | return 0; |
| 263 | } |