src/mainboard/sapphire/pureplatinumh61/devicetree.cb

#
# This file is part of the coreboot project.
#
# Copyright (C) 2017 Nicola Corna <nicola@corna.info>
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#

chip northbridge/intel/sandybridge
	register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
	register "gfx.link_frequency_270_mhz" = "0"
	register "gfx.ndid" = "3"
	register "gfx.use_spread_spectrum_clock" = "0"
	register "gpu_cpu_backlight" = "0x00000000"
	register "gpu_dp_b_hotplug" = "0"
	register "gpu_dp_c_hotplug" = "0"
	register "gpu_dp_d_hotplug" = "0"
	register "gpu_panel_port_select" = "0"
	register "gpu_panel_power_backlight_off_delay" = "0"
	register "gpu_panel_power_backlight_on_delay" = "0"
	register "gpu_panel_power_cycle_delay" = "0"
	register "gpu_panel_power_down_delay" = "0"
	register "gpu_panel_power_up_delay" = "0"
	register "gpu_pch_backlight" = "0x00000000"
	device cpu_cluster 0x0 on
		chip cpu/intel/socket_LGA1155
			device lapic 0x0 on
			end
		end
		chip cpu/intel/model_206ax
			register "c1_acpower" = "1"
			register "c1_battery" = "1"
			register "c2_acpower" = "3"
			register "c2_battery" = "3"
			register "c3_acpower" = "5"
			register "c3_battery" = "5"
			device lapic 0xacac off
			end
		end
	end
	device domain 0x0 on
		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
			register "c2_latency" = "0x0065"
			register "docking_supported" = "0"
			register "gen1_dec" = "0x000c0291"
			register "gen2_dec" = "0x000c0a01"
			register "gen3_dec" = "0x00000000"
			register "gen4_dec" = "0x00000000"
			register "p_cnt_throttling_supported" = "0"
			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
			register "pcie_port_coalesce" = "1"
			register "sata_interface_speed_support" = "0x3"
			register "sata_port_map" = "0x33"
			register "spi.opprefixes" = "{ 0x50, 0x06 }"
			register "spi.ops" = "{ { 0, 1, 0x01 }, { 1, 1, 0x02 }, { 1, 0, 0x03 }, { 0, 0, 0x05 }, { 1, 1, 0x20 }, { 0, 0, 0x9f }, { 0, 1, 0xad }, { 0, 1, 0x04 } }"
			device pci 16.0 on # Management Engine Interface 1
				subsystemid 0x174b 0x1007
			end
			device pci 16.1 off # Management Engine Interface 2
			end
			device pci 16.2 off # Management Engine IDE-R
			end
			device pci 16.3 off # Management Engine KT
			end
			device pci 19.0 off # Intel Gigabit Ethernet
			end
			device pci 1a.0 on # USB2 EHCI #2
				subsystemid 0x174b 0x1007
			end
			device pci 1b.0 on # High Definition Audio Audio controller
				subsystemid 0x8086 0x1c20
			end
			device pci 1c.0 on # PCIe Port #1
				subsystemid 0x174b 0x1007
			end
			device pci 1c.1 off # PCIe Port #2
			end
			device pci 1c.2 off # PCIe Port #3
			end
			device pci 1c.3 off # PCIe Port #4
			end
			device pci 1c.4 on # PCIe Port #5
				subsystemid 0x174b 0x1007
			end
			device pci 1c.5 on # PCIe Port #6
				subsystemid 0x174b 0x1007
			end
			device pci 1c.6 off # PCIe Port #7
			end
			device pci 1c.7 off # PCIe Port #8
			end
			device pci 1d.0 on # USB2 EHCI #1
				subsystemid 0x174b 0x1007
			end
			device pci 1e.0 off # PCI bridge
			end
			device pci 1f.0 on # LPC bridge PCI-LPC bridge
				subsystemid 0x174b 0x1007
				chip superio/fintek/f71808a
					register "multi_function_register_0" = "0x00"
					register "multi_function_register_1" = "0xc4"
					register "multi_function_register_2" = "0x21"
					register "multi_function_register_3" = "0x2f"
					register "multi_function_register_4" = "0x5c"
					register "hwm_peci_tsi_ctrl" = "0x02"	# PECI enabled, 1.23 V
					register "hwm_tcc_temp" = "0x66"	# TCC temperature = 102 °C
					register "hwm_fan1_seg1_speed" = "0xff"	# Fan 1 segment 1 = 100%
					register "hwm_fan1_seg2_speed" = "0xdb"	# Fan 1 segment 2 = 86%
					register "hwm_fan1_seg3_speed" = "0xbc"	# Fan 1 segment 3 = 74%
					register "hwm_fan1_seg4_speed" = "0x9e"	# Fan 1 segment 4 = 62%
					register "hwm_fan1_seg5_speed" = "0x7f"	# Fan 1 segment 5 = 50%
					register "hwm_fan1_temp_src" = "0x18"	# Fan 1 source = PECI
					register "hwm_fan2_seg1_speed" = "0xff"	# Fan 2 segment 1 = 100%
					register "hwm_fan2_seg2_speed" = "0xdb"	# Fan 2 segment 2 = 86%
					register "hwm_fan2_seg3_speed" = "0xbc"	# Fan 2 segment 3 = 74%
					register "hwm_fan2_seg4_speed" = "0x9e"	# Fan 2 segment 4 = 62%
					register "hwm_fan2_seg5_speed" = "0x7f"	# Fan 2 segment 5 = 50%
					register "hwm_fan2_temp_src" = "0x1e"	# Fan 2 source = temperature 2
					device pnp 4e.1 off end	# Serial Port 1
					device pnp 4e.4 on	# Hardware monitor
						io 0x60 = 0x295
						irq 0x70 = 0
					end
					device pnp 4e.5 off end	# Keyboard
					device pnp 4e.6 on	# GPIO
						irq 0xc5 = 0x1f
					end
					device pnp 4e.7 on	# WDT
						io 0x60 = 0xa00
					end
					device pnp 4e.8 off end	# CIR
					device pnp 4e.a on	# PME, ACPI, EUP
						irq 0xe0 = 0x90
						irq 0xf8 = 0x00
						irq 0xf9 = 0x09
						irq 0xfa = 0x00
					end
				end
			end
			device pci 1f.2 on # SATA Controller 1
				subsystemid 0x174b 0x1007
			end
			device pci 1f.3 on # SMBus
				subsystemid 0x174b 0x1007
			end
			device pci 1f.5 off # SATA Controller 2
			end
			device pci 1f.6 off # Thermal
			end
		end
		device pci 00.0 on # Host bridge Host bridge
			subsystemid 0x174b 0x1007
		end
		device pci 01.0 on # PCIe Bridge for discrete graphics
			subsystemid 0x174b 0x1007
		end
		device pci 02.0 on # Internal graphics VGA controller
			subsystemid 0x8086 0x2010
		end
	end
end