blob: 90e1e5d10567b3bc078b70c4479cac820132731c [file] [log] [blame]
John Su8fff2972021-01-21 13:22:58 +08001/* SPDX-License-Identifier: GPL-2.0-only */
2
3/* Driver for BayHub Technology LV2 PCI to SD bridge */
4
5#include <console/console.h>
6#include <device/device.h>
7#include <device/path.h>
8#include <device/pci.h>
9#include <device/pci_ops.h>
10#include <device/pci_ids.h>
11#include "chip.h"
12#include "lv2.h"
13
Victor Ding80b2f232021-02-18 04:27:47 +000014static void lv2_enable(struct device *dev)
John Su8fff2972021-01-21 13:22:58 +080015{
16 struct drivers_generic_bayhub_lv2_config *config = dev->chip_info;
17 pci_dev_init(dev);
18
19 if (!config || !config->enable_power_saving)
20 return;
21 /*
22 * This procedure for enabling power-saving mode is from the
23 * BayHub BIOS Implementation Guideline document.
24 */
25 pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_OFF | LV2_PROTECT_LOCK_OFF);
26 pci_or_config32(dev, LV2_PCR_HEX_FC, LV2_PCIE_PHY_P1_ENABLE);
27 pci_update_config32(dev, LV2_PCR_HEX_E0, LV2_PCI_PM_L1_TIMER_MASK, LV2_PCI_PM_L1_TIMER);
28 pci_update_config32(dev, LV2_PCR_HEX_FC, LV2_ASPM_L1_TIMER_MASK, LV2_ASPM_L1_TIMER);
29 pci_or_config32(dev, LV2_PCR_HEX_A8, LV2_LTR_ENABLE);
30 pci_write_config32(dev, LV2_PCR_HEX_234, LV2_MAX_LATENCY_SETTING);
John Su8fff2972021-01-21 13:22:58 +080031 pci_update_config32(dev, LV2_PCR_HEX_3F4, LV2_L1_SUBSTATE_OPTIMISE_MASK,
32 LV2_L1_SUBSTATE_OPTIMISE);
John Su8fff2972021-01-21 13:22:58 +080033 pci_update_config32(dev, LV2_PCR_HEX_300, LV2_TUNING_WINDOW_MASK, LV2_TUNING_WINDOW);
34 pci_update_config32(dev, LV2_PCR_HEX_304, LV2_DRIVER_STRENGTH_MASK,
35 LV2_DRIVER_STRENGTH);
36 pci_update_config32(dev, LV2_PCR_HEX_308, LV2_RESET_DMA_DISABLE_MASK,
37 LV2_RESET_DMA_DISABLE);
John Su8fff2972021-01-21 13:22:58 +080038 pci_write_config32(dev, LV2_PROTECT, LV2_PROTECT_ON | LV2_PROTECT_LOCK_ON);
Victor Dinge0c2c062021-02-18 07:25:08 +000039 printk(BIOS_INFO, "BayHub LV2: Power-saving enabled\n");
John Su8fff2972021-01-21 13:22:58 +080040}
41
42static struct device_operations lv2_ops = {
43 .read_resources = pci_dev_read_resources,
44 .set_resources = pci_dev_set_resources,
45 .enable_resources = pci_dev_enable_resources,
46 .ops_pci = &pci_dev_ops_pci,
Victor Ding80b2f232021-02-18 04:27:47 +000047 .enable = lv2_enable,
John Su8fff2972021-01-21 13:22:58 +080048};
49
50static const unsigned short pci_device_ids[] = {
51 PCI_DEVICE_ID_O2_LV2,
52 0
53};
54
55static const struct pci_driver bayhub_lv2 __pci_driver = {
56 .ops = &lv2_ops,
57 .vendor = PCI_VENDOR_ID_O2,
58 .devices = pci_device_ids,
59};
60
61struct chip_operations drivers_generic_bayhub_lv2_ops = {
62 CHIP_NAME("BayHub Technology LV2 PCIe to SD bridge")
63};