Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
Furquan Shaikh | 76cedd2 | 2020-05-02 10:24:23 -0700 | [diff] [blame] | 4 | #include <acpi/acpi.h> |
Felix Held | 928a9c8 | 2022-02-24 00:51:11 +0100 | [diff] [blame] | 5 | #include <arch/hpet.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 7 | #include <stdint.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 8 | #include <cpu/intel/model_2065x/model_2065x.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 9 | #include <device/device.h> |
| 10 | #include <device/pci.h> |
| 11 | #include <device/pci_ids.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 12 | #include "chip.h" |
Arthur Heymans | 6473473 | 2021-01-18 00:30:23 +0100 | [diff] [blame] | 13 | #include <commonlib/bsd/helpers.h> |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 14 | #include "ironlake.h" |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 15 | #include <cpu/intel/smm_reloc.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 16 | |
| 17 | static int bridge_revision_id = -1; |
| 18 | |
| 19 | int bridge_silicon_revision(void) |
| 20 | { |
| 21 | if (bridge_revision_id < 0) { |
Angel Pons | 43bcc7b | 2020-06-22 18:11:31 +0200 | [diff] [blame] | 22 | uint8_t stepping = cpuid_eax(1) & 0x0f; |
| 23 | uint8_t bridge_id = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); |
| 24 | bridge_revision_id = (bridge_id & 0xf0) | stepping; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 25 | } |
| 26 | return bridge_revision_id; |
| 27 | } |
| 28 | |
Angel Pons | 43bcc7b | 2020-06-22 18:11:31 +0200 | [diff] [blame] | 29 | /* |
| 30 | * Reserve everything between A segment and 1MB: |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 31 | * |
| 32 | * 0xa0000 - 0xbffff: legacy VGA |
| 33 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 34 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 35 | */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 36 | |
| 37 | static void add_fixed_resources(struct device *dev, int index) |
| 38 | { |
| 39 | struct resource *resource; |
| 40 | |
| 41 | /* 0xe0000000-0xf0000000 PCIe config. |
| 42 | 0xfed10000-0xfed14000 MCH |
| 43 | 0xfed17000-0xfed18000 HECI |
| 44 | 0xfed18000-0xfed19000 DMI |
| 45 | 0xfed19000-0xfed1a000 EPBAR |
| 46 | 0xfed1c000-0xfed20000 RCBA |
| 47 | 0xfed90000-0xfed94000 IOMMU |
| 48 | 0xff800000-0xffffffff ROM. */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 49 | |
| 50 | resource = new_resource(dev, index++); |
Elyes Haouas | 3a99807 | 2022-11-18 15:11:02 +0100 | [diff] [blame] | 51 | resource->base = (resource_t)HPET_BASE_ADDRESS; |
| 52 | resource->size = (resource_t)0x00100000; |
Angel Pons | 43bcc7b | 2020-06-22 18:11:31 +0200 | [diff] [blame] | 53 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED | |
| 54 | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 55 | |
Kyösti Mälkki | 8ee11b3 | 2021-06-27 21:08:32 +0300 | [diff] [blame] | 56 | mmio_from_to(dev, index++, 0xa0000, 0xc0000); |
| 57 | reserved_ram_from_to(dev, index++, 0xc0000, 1 * MiB); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 58 | } |
| 59 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 60 | #if CONFIG(HAVE_ACPI_TABLES) |
Patrick Rudolph | 5c3452b | 2018-05-15 11:37:26 +0200 | [diff] [blame] | 61 | static const char *northbridge_acpi_name(const struct device *dev) |
| 62 | { |
| 63 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 64 | return "PCI0"; |
| 65 | |
Fabio Aiuto | 61ed4ef | 2022-09-30 14:55:53 +0200 | [diff] [blame] | 66 | if (!is_pci_dev_on_bus(dev, 0)) |
Patrick Rudolph | 5c3452b | 2018-05-15 11:37:26 +0200 | [diff] [blame] | 67 | return NULL; |
| 68 | |
| 69 | switch (dev->path.pci.devfn) { |
| 70 | case PCI_DEVFN(0, 0): |
| 71 | return "MCHC"; |
| 72 | } |
| 73 | |
| 74 | return NULL; |
| 75 | } |
| 76 | #endif |
| 77 | |
Arthur Heymans | 62eb94c | 2022-11-07 08:34:41 +0100 | [diff] [blame] | 78 | struct device_operations ironlake_pci_domain_ops = { |
Angel Pons | 43bcc7b | 2020-06-22 18:11:31 +0200 | [diff] [blame] | 79 | .read_resources = pci_domain_read_resources, |
| 80 | .set_resources = pci_domain_set_resources, |
| 81 | .scan_bus = pci_domain_scan_bus, |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 82 | #if CONFIG(HAVE_ACPI_TABLES) |
Angel Pons | 43bcc7b | 2020-06-22 18:11:31 +0200 | [diff] [blame] | 83 | .acpi_name = northbridge_acpi_name, |
Patrick Rudolph | 5c3452b | 2018-05-15 11:37:26 +0200 | [diff] [blame] | 84 | #endif |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 85 | }; |
| 86 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame] | 87 | static void mc_read_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 88 | { |
Nico Huber | 308540d | 2020-09-13 21:59:14 +0200 | [diff] [blame] | 89 | uint32_t tseg_base, tseg_end; |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 90 | uint64_t touud; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 91 | uint16_t reg16; |
Nico Huber | 08e8e47 | 2020-09-13 21:56:50 +0200 | [diff] [blame] | 92 | int index = 3; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 93 | |
| 94 | pci_dev_read_resources(dev); |
| 95 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 96 | mmconf_resource(dev, 0x50); |
| 97 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 98 | tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); |
Nico Huber | 308540d | 2020-09-13 21:59:14 +0200 | [diff] [blame] | 99 | tseg_end = tseg_base + CONFIG_SMM_TSEG_SIZE; |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 100 | touud = pci_read_config16(pcidev_on_root(0, 0), |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 101 | TOUUD); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 102 | |
| 103 | printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 104 | printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 105 | |
| 106 | /* Report the memory regions */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 107 | ram_resource_kb(dev, index++, 0, 0xa0000 / KiB); |
| 108 | ram_resource_kb(dev, index++, 1 * MiB / KiB, (tseg_base - 1 * MiB) / KiB); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 109 | |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 110 | mmio_resource_kb(dev, index++, tseg_base / KiB, CONFIG_SMM_TSEG_SIZE / KiB); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 111 | |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 112 | reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 113 | const int uma_sizes_gtt[16] = |
| 114 | { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; |
| 115 | /* Igd memory */ |
| 116 | const int uma_sizes_igd[16] = { |
| 117 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 |
| 118 | }; |
| 119 | u32 igd_base, gtt_base; |
| 120 | int uma_size_igd, uma_size_gtt; |
| 121 | |
| 122 | uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF]; |
| 123 | uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; |
| 124 | |
| 125 | igd_base = |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 126 | pci_read_config32(pcidev_on_root(0, 0), IGD_BASE); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 127 | gtt_base = |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 128 | pci_read_config32(pcidev_on_root(0, 0), GTT_BASE); |
Nico Huber | 308540d | 2020-09-13 21:59:14 +0200 | [diff] [blame] | 129 | if (gtt_base > tseg_end) { |
| 130 | /* Reserve the gap. MMIO doesn't work in this range. Keep |
| 131 | it uncacheable, though, for easier MTRR allocation. */ |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 132 | mmio_resource_kb(dev, index++, tseg_end / KiB, (gtt_base - tseg_end) / KiB); |
Nico Huber | 308540d | 2020-09-13 21:59:14 +0200 | [diff] [blame] | 133 | } |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 134 | mmio_resource_kb(dev, index++, gtt_base / KiB, uma_size_gtt * KiB); |
| 135 | mmio_resource_kb(dev, index++, igd_base / KiB, uma_size_igd * KiB); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 136 | |
Kyösti Mälkki | 0a18d64 | 2021-06-28 21:43:31 +0300 | [diff] [blame] | 137 | upper_ram_end(dev, index++, touud * MiB); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 138 | |
| 139 | /* This memory is not DMA-capable. */ |
Angel Pons | 9333b74 | 2020-07-22 16:04:15 +0200 | [diff] [blame] | 140 | if (touud >= 8192 - 64) |
Kyösti Mälkki | 27d6299 | 2022-05-24 20:25:58 +0300 | [diff] [blame] | 141 | bad_ram_resource_kb(dev, index++, 0x1fc000000ULL / KiB, 0x004000000 / KiB); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 142 | |
Nico Huber | 08e8e47 | 2020-09-13 21:56:50 +0200 | [diff] [blame] | 143 | add_fixed_resources(dev, index); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 144 | } |
| 145 | |
Angel Pons | ecdbc84 | 2020-06-22 17:28:42 +0200 | [diff] [blame] | 146 | static void northbridge_init(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 147 | { |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 148 | /* Clear error status bits */ |
Angel Pons | dea722b | 2021-03-26 14:11:12 +0100 | [diff] [blame] | 149 | dmibar_write32(DMIUESTS, 0xffffffff); |
| 150 | dmibar_write32(DMICESTS, 0xffffffff); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 151 | |
Angel Pons | dea722b | 2021-03-26 14:11:12 +0100 | [diff] [blame] | 152 | dmibar_setbits32(DMILLTC, 1 << 29); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 153 | |
Angel Pons | dea722b | 2021-03-26 14:11:12 +0100 | [diff] [blame] | 154 | dmibar_setbits32(0x1f8, 1 << 16); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 155 | |
Angel Pons | dea722b | 2021-03-26 14:11:12 +0100 | [diff] [blame] | 156 | dmibar_setbits32(DMILCTL, 1 << 1 | 1 << 0); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 157 | } |
| 158 | |
Arthur Heymans | 28bca05 | 2019-10-01 21:20:33 +0200 | [diff] [blame] | 159 | /* Disable unused PEG devices based on devicetree before PCI enumeration */ |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 160 | static void ironlake_init(void *const chip_info) |
Arthur Heymans | 28bca05 | 2019-10-01 21:20:33 +0200 | [diff] [blame] | 161 | { |
| 162 | u32 deven_mask = UINT32_MAX; |
| 163 | const struct device *dev; |
| 164 | |
| 165 | dev = pcidev_on_root(1, 0); |
| 166 | if (!dev || !dev->enabled) { |
| 167 | printk(BIOS_DEBUG, "Disabling PEG10.\n"); |
| 168 | deven_mask &= ~DEVEN_PEG10; |
| 169 | } |
| 170 | dev = pcidev_on_root(2, 0); |
| 171 | if (!dev || !dev->enabled) { |
| 172 | printk(BIOS_DEBUG, "Disabling IGD.\n"); |
| 173 | deven_mask &= ~DEVEN_IGD; |
| 174 | } |
| 175 | const struct device *const d0f0 = pcidev_on_root(0, 0); |
| 176 | if (d0f0) |
Angel Pons | 16fe1e0 | 2020-07-22 16:12:33 +0200 | [diff] [blame] | 177 | pci_update_config32(d0f0, DEVEN, deven_mask, 0); |
Arthur Heymans | 28bca05 | 2019-10-01 21:20:33 +0200 | [diff] [blame] | 178 | |
| 179 | } |
| 180 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 181 | static struct device_operations mc_ops = { |
Angel Pons | 43bcc7b | 2020-06-22 18:11:31 +0200 | [diff] [blame] | 182 | .read_resources = mc_read_resources, |
| 183 | .set_resources = pci_dev_set_resources, |
| 184 | .enable_resources = pci_dev_enable_resources, |
| 185 | .init = northbridge_init, |
| 186 | .acpi_fill_ssdt = generate_cpu_entries, |
| 187 | .ops_pci = &pci_dev_ops_pci, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 188 | }; |
| 189 | |
Angel Pons | 6642b44 | 2020-09-21 21:03:46 +0200 | [diff] [blame] | 190 | /* |
| 191 | * The host bridge PCI device ID can be changed by the firmware. There |
| 192 | * is no documentation about it, though. There's 'official' IDs, which |
| 193 | * appear in spec updates and Windows drivers, and 'mysterious' IDs, |
| 194 | * which Intel doesn't want OSes to know about and thus are not listed. |
| 195 | * |
| 196 | * The current coreboot code seems to be able to change the device ID |
| 197 | * of the host bridge, but it seems to be missing a warm reset so that |
| 198 | * the device ID changes. Account for the 'mysterious' device IDs in |
| 199 | * the northbridge driver, so that booting an OS has a chance to work. |
| 200 | */ |
| 201 | static const unsigned short pci_device_ids[] = { |
| 202 | /* 'Official' DIDs */ |
| 203 | 0x0040, /* Clarkdale */ |
| 204 | 0x0044, /* Arrandale */ |
| 205 | 0x0048, /* Unknown, but it appears in OS drivers and raminit */ |
| 206 | |
| 207 | /* Mysterious DIDs, taken from Linux' intel-agp driver */ |
| 208 | 0x0062, /* Arrandale A-? */ |
| 209 | 0x0069, /* Clarkdale K-0 */ |
| 210 | 0x006a, /* Arrandale K-0 */ |
| 211 | 0 |
| 212 | }; |
| 213 | |
| 214 | static const struct pci_driver mc_driver_ilk __pci_driver = { |
| 215 | .ops = &mc_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 216 | .vendor = PCI_VID_INTEL, |
Angel Pons | 6642b44 | 2020-09-21 21:03:46 +0200 | [diff] [blame] | 217 | .devices = pci_device_ids, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 218 | }; |
| 219 | |
Arthur Heymans | 62eb94c | 2022-11-07 08:34:41 +0100 | [diff] [blame] | 220 | struct device_operations ironlake_cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 221 | .read_resources = noop_read_resources, |
| 222 | .set_resources = noop_set_resources, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 223 | .init = mp_cpu_bus_init, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 224 | }; |
| 225 | |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 226 | struct chip_operations northbridge_intel_ironlake_ops = { |
Angel Pons | 9d7431c | 2020-10-22 23:55:39 +0200 | [diff] [blame] | 227 | CHIP_NAME("Intel Ironlake integrated Northbridge") |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 228 | .init = ironlake_init, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 229 | }; |