Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * Copyright (C) 2013 Vladimir Serbinenko |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <arch/acpi.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <stdint.h> |
| 22 | #include <delay.h> |
| 23 | #include <cpu/intel/model_2065x/model_2065x.h> |
| 24 | #include <cpu/x86/msr.h> |
| 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <device/device.h> |
| 27 | #include <device/pci.h> |
| 28 | #include <device/pci_ids.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 29 | #include <stdlib.h> |
| 30 | #include <string.h> |
| 31 | #include <cpu/cpu.h> |
| 32 | #include <cbmem.h> |
| 33 | #include "chip.h" |
| 34 | #include "nehalem.h" |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 35 | #include <cpu/intel/smm/gen1/smi.h> |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 36 | |
| 37 | static int bridge_revision_id = -1; |
| 38 | |
| 39 | int bridge_silicon_revision(void) |
| 40 | { |
| 41 | if (bridge_revision_id < 0) { |
| 42 | uint8_t stepping = cpuid_eax(1) & 0xf; |
| 43 | uint8_t bridge_id = |
| 44 | pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), |
| 45 | PCI_DEVICE_ID) & 0xf0; |
| 46 | bridge_revision_id = bridge_id | stepping; |
| 47 | } |
| 48 | return bridge_revision_id; |
| 49 | } |
| 50 | |
| 51 | /* Reserve everything between A segment and 1MB: |
| 52 | * |
| 53 | * 0xa0000 - 0xbffff: legacy VGA |
| 54 | * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel) |
| 55 | * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI |
| 56 | */ |
| 57 | static const int legacy_hole_base_k = 0xa0000 / 1024; |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 58 | |
| 59 | static void add_fixed_resources(struct device *dev, int index) |
| 60 | { |
| 61 | struct resource *resource; |
| 62 | |
| 63 | /* 0xe0000000-0xf0000000 PCIe config. |
| 64 | 0xfed10000-0xfed14000 MCH |
| 65 | 0xfed17000-0xfed18000 HECI |
| 66 | 0xfed18000-0xfed19000 DMI |
| 67 | 0xfed19000-0xfed1a000 EPBAR |
| 68 | 0xfed1c000-0xfed20000 RCBA |
| 69 | 0xfed90000-0xfed94000 IOMMU |
| 70 | 0xff800000-0xffffffff ROM. */ |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 71 | |
| 72 | resource = new_resource(dev, index++); |
| 73 | resource->base = (resource_t) 0xfed00000; |
| 74 | resource->size = (resource_t) 0x00100000; |
| 75 | resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | |
| 76 | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; |
| 77 | |
| 78 | mmio_resource(dev, index++, legacy_hole_base_k, |
| 79 | (0xc0000 >> 10) - legacy_hole_base_k); |
| 80 | reserved_ram_resource(dev, index++, 0xc0000 >> 10, |
| 81 | (0x100000 - 0xc0000) >> 10); |
| 82 | |
Martin Roth | 3323260 | 2017-06-24 14:48:50 -0600 | [diff] [blame] | 83 | #if IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 84 | reserved_ram_resource(dev, index++, |
| 85 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
| 86 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
| 87 | #endif |
| 88 | } |
| 89 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame^] | 90 | static void pci_domain_set_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 91 | { |
| 92 | assign_resources(dev->link_list); |
| 93 | } |
| 94 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 95 | static struct device_operations pci_domain_ops = { |
| 96 | .read_resources = pci_domain_read_resources, |
| 97 | .set_resources = pci_domain_set_resources, |
| 98 | .enable_resources = NULL, |
| 99 | .init = NULL, |
| 100 | .scan_bus = pci_domain_scan_bus, |
| 101 | .ops_pci_bus = pci_bus_default_ops, |
| 102 | }; |
| 103 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame^] | 104 | static void mc_read_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 105 | { |
| 106 | uint32_t tseg_base; |
| 107 | uint64_t TOUUD; |
| 108 | uint16_t reg16; |
| 109 | |
| 110 | pci_dev_read_resources(dev); |
| 111 | |
Kyösti Mälkki | e25b5ef | 2016-12-02 08:56:05 +0200 | [diff] [blame] | 112 | mmconf_resource(dev, 0x50); |
| 113 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 114 | tseg_base = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); |
| 115 | TOUUD = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), |
| 116 | D0F0_TOUUD); |
| 117 | |
| 118 | printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); |
| 119 | printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned)TOUUD); |
| 120 | |
| 121 | /* Report the memory regions */ |
| 122 | ram_resource(dev, 3, 0, 640); |
| 123 | ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768)); |
| 124 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 125 | mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); |
| 126 | |
| 127 | reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); |
| 128 | const int uma_sizes_gtt[16] = |
| 129 | { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; |
| 130 | /* Igd memory */ |
| 131 | const int uma_sizes_igd[16] = { |
| 132 | 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352, 256, 512 |
| 133 | }; |
| 134 | u32 igd_base, gtt_base; |
| 135 | int uma_size_igd, uma_size_gtt; |
| 136 | |
| 137 | uma_size_igd = uma_sizes_igd[(reg16 >> 4) & 0xF]; |
| 138 | uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; |
| 139 | |
| 140 | igd_base = |
| 141 | pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_IGD_BASE); |
| 142 | gtt_base = |
| 143 | pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GTT_BASE); |
| 144 | mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); |
| 145 | mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); |
| 146 | |
| 147 | if (TOUUD > 4096) |
| 148 | ram_resource(dev, 8, (4096 << 10), ((TOUUD - 4096) << 10)); |
| 149 | |
| 150 | /* This memory is not DMA-capable. */ |
| 151 | if (TOUUD >= 8192 - 64) |
| 152 | bad_ram_resource(dev, 9, 0x1fc000000ULL >> 10, 0x004000000 >> 10); |
| 153 | |
| 154 | add_fixed_resources(dev, 10); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 155 | } |
| 156 | |
Nico Huber | 6f8b7df | 2016-10-08 18:42:46 +0200 | [diff] [blame] | 157 | u32 northbridge_get_tseg_base(void) |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 158 | { |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame^] | 159 | struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 160 | |
Nico Huber | 6f8b7df | 2016-10-08 18:42:46 +0200 | [diff] [blame] | 161 | return pci_read_config32(dev, TSEG) & ~1; |
Vladimir Serbinenko | 0f9aa1c | 2015-05-29 16:52:50 +0200 | [diff] [blame] | 162 | } |
| 163 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame^] | 164 | static void mc_set_resources(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 165 | { |
| 166 | /* And call the normal set_resources */ |
| 167 | pci_dev_set_resources(dev); |
| 168 | } |
| 169 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame^] | 170 | static void intel_set_subsystem(struct device *dev, unsigned vendor, unsigned device) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 171 | { |
| 172 | if (!vendor || !device) { |
| 173 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 174 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 175 | } else { |
| 176 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 177 | ((device & 0xffff) << 16) | (vendor & |
| 178 | 0xffff)); |
| 179 | } |
| 180 | } |
| 181 | |
| 182 | static void northbridge_dmi_init(struct device *dev) |
| 183 | { |
| 184 | u32 reg32; |
| 185 | |
| 186 | /* Clear error status bits */ |
| 187 | DMIBAR32(0x1c4) = 0xffffffff; |
| 188 | DMIBAR32(0x1d0) = 0xffffffff; |
| 189 | |
| 190 | /* Steps prior to DMI ASPM */ |
| 191 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 192 | reg32 = DMIBAR32(0x250); |
| 193 | reg32 &= ~((1 << 22) | (1 << 20)); |
| 194 | reg32 |= (1 << 21); |
| 195 | DMIBAR32(0x250) = reg32; |
| 196 | } |
| 197 | |
| 198 | reg32 = DMIBAR32(0x238); |
| 199 | reg32 |= (1 << 29); |
| 200 | DMIBAR32(0x238) = reg32; |
| 201 | |
| 202 | if (bridge_silicon_revision() >= SNB_STEP_D0) { |
| 203 | reg32 = DMIBAR32(0x1f8); |
| 204 | reg32 |= (1 << 16); |
| 205 | DMIBAR32(0x1f8) = reg32; |
| 206 | } else if (bridge_silicon_revision() >= SNB_STEP_D1) { |
| 207 | reg32 = DMIBAR32(0x1f8); |
| 208 | reg32 &= ~(1 << 26); |
| 209 | reg32 |= (1 << 16); |
| 210 | DMIBAR32(0x1f8) = reg32; |
| 211 | |
| 212 | reg32 = DMIBAR32(0x1fc); |
| 213 | reg32 |= (1 << 12) | (1 << 23); |
| 214 | DMIBAR32(0x1fc) = reg32; |
| 215 | } |
| 216 | |
| 217 | /* Enable ASPM on SNB link, should happen before PCH link */ |
| 218 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { |
| 219 | reg32 = DMIBAR32(0xd04); |
| 220 | reg32 |= (1 << 4); |
| 221 | DMIBAR32(0xd04) = reg32; |
| 222 | } |
| 223 | |
| 224 | reg32 = DMIBAR32(0x88); |
| 225 | reg32 |= (1 << 1) | (1 << 0); |
| 226 | DMIBAR32(0x88) = reg32; |
| 227 | } |
| 228 | |
| 229 | static void northbridge_init(struct device *dev) |
| 230 | { |
| 231 | u8 bios_reset_cpl; |
| 232 | u32 bridge_type; |
| 233 | |
| 234 | northbridge_dmi_init(dev); |
| 235 | |
| 236 | bridge_type = MCHBAR32(0x5f10); |
| 237 | bridge_type &= ~0xff; |
| 238 | |
| 239 | if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) { |
| 240 | /* Enable Power Aware Interrupt Routing */ |
| 241 | u8 pair = MCHBAR8(0x5418); |
| 242 | pair &= ~0xf; /* Clear 3:0 */ |
| 243 | pair |= 0x4; /* Fixed Priority */ |
| 244 | MCHBAR8(0x5418) = pair; |
| 245 | |
| 246 | /* 30h for IvyBridge */ |
| 247 | bridge_type |= 0x30; |
| 248 | } else { |
| 249 | /* 20h for Sandybridge */ |
| 250 | bridge_type |= 0x20; |
| 251 | } |
| 252 | MCHBAR32(0x5f10) = bridge_type; |
| 253 | |
| 254 | /* |
| 255 | * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU |
| 256 | * that BIOS has initialized memory and power management |
| 257 | */ |
| 258 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
| 259 | bios_reset_cpl |= 1; |
| 260 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 261 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 262 | |
| 263 | /* Configure turbo power limits 1ms after reset complete bit */ |
| 264 | mdelay(1); |
| 265 | #ifdef DISABLED |
| 266 | set_power_limits(28); |
| 267 | |
| 268 | /* |
| 269 | * CPUs with configurable TDP also need power limits set |
| 270 | * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT. |
| 271 | */ |
| 272 | if (cpu_config_tdp_levels()) { |
| 273 | msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT); |
| 274 | MCHBAR32(0x59A0) = msr.lo; |
| 275 | MCHBAR32(0x59A4) = msr.hi; |
| 276 | } |
| 277 | #endif |
| 278 | /* Set here before graphics PM init */ |
| 279 | MCHBAR32(0x5500) = 0x00100001; |
| 280 | } |
| 281 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 282 | static struct pci_operations intel_pci_ops = { |
| 283 | .set_subsystem = intel_set_subsystem, |
| 284 | }; |
| 285 | |
| 286 | static struct device_operations mc_ops = { |
| 287 | .read_resources = mc_read_resources, |
| 288 | .set_resources = mc_set_resources, |
| 289 | .enable_resources = pci_dev_enable_resources, |
| 290 | .init = northbridge_init, |
Vladimir Serbinenko | 0a66991 | 2014-10-05 14:34:17 +0200 | [diff] [blame] | 291 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 292 | .scan_bus = 0, |
| 293 | .ops_pci = &intel_pci_ops, |
| 294 | }; |
| 295 | |
| 296 | static const struct pci_driver mc_driver_44 __pci_driver = { |
| 297 | .ops = &mc_ops, |
| 298 | .vendor = PCI_VENDOR_ID_INTEL, |
| 299 | .device = 0x0044, /* Nehalem */ |
| 300 | }; |
| 301 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame^] | 302 | static void cpu_bus_init(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 303 | { |
| 304 | initialize_cpus(dev->link_list); |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 305 | } |
| 306 | |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 307 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 308 | .read_resources = DEVICE_NOOP, |
| 309 | .set_resources = DEVICE_NOOP, |
| 310 | .enable_resources = DEVICE_NOOP, |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 311 | .init = cpu_bus_init, |
| 312 | .scan_bus = 0, |
| 313 | }; |
| 314 | |
Elyes HAOUAS | 706aabc | 2018-02-09 08:49:32 +0100 | [diff] [blame^] | 315 | static void enable_dev(struct device *dev) |
Vladimir Serbinenko | c6f6be0 | 2013-11-12 22:32:08 +0100 | [diff] [blame] | 316 | { |
| 317 | /* Set the operations if it is a special bus type */ |
| 318 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 319 | dev->ops = &pci_domain_ops; |
| 320 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 321 | dev->ops = &cpu_bus_ops; |
| 322 | } |
| 323 | } |
| 324 | |
| 325 | struct chip_operations northbridge_intel_nehalem_ops = { |
| 326 | CHIP_NAME("Intel i7 (Nehalem) integrated Northbridge") |
| 327 | .enable_dev = enable_dev, |
| 328 | }; |