Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 17 | * Foundation, Inc. |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <arch/io.h> |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 24 | #include <cpu/x86/msr.h> |
| 25 | #include <cpu/amd/mtrr.h> |
| 26 | #include <device/pci_def.h> |
Paul Menzel | 22bbb69 | 2013-03-29 15:39:54 +0100 | [diff] [blame] | 27 | #include <southbridge/amd/cimx/cimx_util.h> |
Felix Held | dfb53ef | 2015-10-11 13:24:40 +0200 | [diff] [blame^] | 28 | #include "SBPLATFORM.h" |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 29 | |
| 30 | //#define SMBUS_IO_BASE 0x6000 |
Paul Menzel | a4b802c | 2013-03-06 18:42:02 +0100 | [diff] [blame] | 31 | void set_pcie_reset(void); |
| 32 | void set_pcie_dereset(void); |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 33 | |
| 34 | /** |
| 35 | * TODO |
| 36 | * SB CIMx callback |
| 37 | */ |
| 38 | void set_pcie_reset(void) |
| 39 | { |
| 40 | } |
| 41 | |
| 42 | /** |
| 43 | * TODO |
| 44 | * mainboard specific SB CIMx callback |
| 45 | */ |
| 46 | void set_pcie_dereset(void) |
| 47 | { |
| 48 | } |
| 49 | |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 50 | |
Jens Rottmann | 5e70766 | 2013-02-26 15:56:11 +0100 | [diff] [blame] | 51 | /********************************************** |
| 52 | * Enable the dedicated functions of the board. |
| 53 | **********************************************/ |
Paul Menzel | 528640d | 2013-02-23 21:31:23 +0100 | [diff] [blame] | 54 | static void mainboard_enable(device_t dev) |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 55 | { |
Scott Duplichan | 63896e7 | 2011-02-26 17:49:49 +0000 | [diff] [blame] | 56 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
Jens Rottmann | db6c5bf | 2013-03-21 22:21:28 +0100 | [diff] [blame] | 57 | |
Felix Held | dfb53ef | 2015-10-11 13:24:40 +0200 | [diff] [blame^] | 58 | /* Power off unused clock pins of GPP PCIe devices */ |
| 59 | u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); |
| 60 | /* |
| 61 | * GPP CLK0 connected to unpopulated mini PCIe slot |
| 62 | * GPP CLK1 connected to ethernet chip |
| 63 | */ |
| 64 | write8(misc_mem_clk_cntrl + 0, 0xFF); |
| 65 | /* GPP CLK2 connected to the external USB3 controller */ |
| 66 | write8(misc_mem_clk_cntrl + 1, 0x0F); |
| 67 | write8(misc_mem_clk_cntrl + 2, 0x00); |
| 68 | write8(misc_mem_clk_cntrl + 3, 0x00); |
| 69 | /* SLT_GFX_CLK connected to PCIe slot */ |
| 70 | write8(misc_mem_clk_cntrl + 4, 0xF0); |
| 71 | |
Jens Rottmann | db6c5bf | 2013-03-21 22:21:28 +0100 | [diff] [blame] | 72 | /* |
| 73 | * Initialize ASF registers to an arbitrary address because someone |
| 74 | * long ago set things up this way inside the SPD read code. The |
| 75 | * SPD read code has been made generic and moved out of the board |
| 76 | * directory, so the ASF init is being done here. |
| 77 | */ |
| 78 | pm_iowrite(0x29, 0x80); |
| 79 | pm_iowrite(0x28, 0x61); |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 80 | } |
| 81 | |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 82 | struct chip_operations mainboard_ops = { |
Paul Menzel | 528640d | 2013-02-23 21:31:23 +0100 | [diff] [blame] | 83 | .enable_dev = mainboard_enable, |
Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame] | 84 | }; |