Scott Duplichan | a649a96 | 2011-02-24 05:00:33 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <console/console.h> |
| 21 | #include <device/device.h> |
| 22 | #include <device/pci.h> |
| 23 | #include <arch/io.h> |
| 24 | #include <boot/tables.h> |
| 25 | #include <cpu/x86/msr.h> |
| 26 | #include <cpu/amd/mtrr.h> |
| 27 | #include <device/pci_def.h> |
| 28 | //#include <southbridge/amd/sb800/sb800.h> |
| 29 | #include "chip.h" |
| 30 | |
| 31 | //#define SMBUS_IO_BASE 0x6000 |
| 32 | |
| 33 | /** |
| 34 | * TODO |
| 35 | * SB CIMx callback |
| 36 | */ |
| 37 | void set_pcie_reset(void) |
| 38 | { |
| 39 | } |
| 40 | |
| 41 | /** |
| 42 | * TODO |
| 43 | * mainboard specific SB CIMx callback |
| 44 | */ |
| 45 | void set_pcie_dereset(void) |
| 46 | { |
| 47 | } |
| 48 | |
| 49 | uint64_t uma_memory_base, uma_memory_size; |
| 50 | |
| 51 | /************************************************* |
| 52 | * enable the dedicated function in persimmon board. |
| 53 | *************************************************/ |
| 54 | static void persimmon_enable(device_t dev) |
| 55 | { |
| 56 | printk(BIOS_INFO, "Mainboard Persimmon Enable. dev=0x%p\n", dev); |
| 57 | #if (CONFIG_GFXUMA == 1) |
| 58 | msr_t msr, msr2; |
| 59 | uint32_t sys_mem; |
| 60 | |
| 61 | /* TOP_MEM: the top of DRAM below 4G */ |
| 62 | msr = rdmsr(TOP_MEM); |
| 63 | printk |
| 64 | (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", |
| 65 | __func__, msr.lo, msr.hi); |
| 66 | |
| 67 | /* TOP_MEM2: the top of DRAM above 4G */ |
| 68 | msr2 = rdmsr(TOP_MEM2); |
| 69 | printk |
| 70 | (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", |
| 71 | __func__, msr2.lo, msr2.hi); |
| 72 | |
| 73 | /* refer to UMA Size Consideration in Family14h BKDG. */ |
| 74 | sys_mem = msr.lo + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size, refer MemNGetUmaSizeON() |
| 75 | if ((msr.hi & 0x0000000F) || (sys_mem >= 0x80000000)) { |
| 76 | uma_memory_size = 0x18000000; /* >= 2G memory, 384M recommended UMA */ |
| 77 | } |
| 78 | else { |
| 79 | if (sys_mem >= 0x40000000) { |
| 80 | uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ |
| 81 | } |
| 82 | else { |
| 83 | uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ |
| 84 | } |
| 85 | } |
| 86 | |
| 87 | uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ |
| 88 | printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", |
| 89 | __func__, uma_memory_size, uma_memory_base); |
| 90 | |
| 91 | /* TODO: TOP_MEM2 */ |
| 92 | #else |
| 93 | uma_memory_size = 0x10000000; /* 256M recommended UMA */ |
| 94 | uma_memory_base = 0x30000000; /* 1GB system memory supported */ |
| 95 | #endif |
| 96 | |
| 97 | } |
| 98 | |
| 99 | int add_mainboard_resources(struct lb_memory *mem) |
| 100 | { |
| 101 | /* UMA is removed from system memory in the northbridge code, but |
| 102 | * in some circumstances we want the memory mentioned as reserved. |
| 103 | */ |
| 104 | #if (CONFIG_GFXUMA == 1) |
| 105 | printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", |
| 106 | uma_memory_base, uma_memory_size); |
| 107 | lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, |
| 108 | uma_memory_size); |
| 109 | #endif |
| 110 | return 0; |
| 111 | } |
| 112 | struct chip_operations mainboard_ops = { |
| 113 | CHIP_NAME("AMD PERSIMMON Mainboard") |
| 114 | .enable_dev = persimmon_enable, |
| 115 | }; |