Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
| 4 | #include <cpu/x86/msr.h> |
| 5 | #include <cpu/x86/mtrr.h> |
| 6 | #include <cpu/amd/mtrr.h> |
| 7 | #include <cpu/x86/cache.h> |
| 8 | #include <string.h> |
Kyösti Mälkki | d4955f0 | 2017-09-08 07:14:17 +0300 | [diff] [blame] | 9 | #include <northbridge/amd/agesa/agesa_helper.h> |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 10 | |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 11 | /* TODO: Do we want MTRR_DEF_TYPE_MSR too? */ |
| 12 | static const uint32_t msr_backup[] = { |
| 13 | MTRR_FIX_64K_00000, |
| 14 | MTRR_FIX_16K_80000, |
| 15 | MTRR_FIX_16K_A0000, |
| 16 | MTRR_FIX_4K_C0000, |
| 17 | MTRR_FIX_4K_C8000, |
| 18 | MTRR_FIX_4K_D0000, |
| 19 | MTRR_FIX_4K_D8000, |
| 20 | MTRR_FIX_4K_E0000, |
| 21 | MTRR_FIX_4K_E8000, |
| 22 | MTRR_FIX_4K_F0000, |
| 23 | MTRR_FIX_4K_F8000, |
| 24 | MTRR_PHYS_BASE(0), |
| 25 | MTRR_PHYS_MASK(0), |
| 26 | MTRR_PHYS_BASE(1), |
| 27 | MTRR_PHYS_MASK(1), |
| 28 | MTRR_PHYS_BASE(2), |
| 29 | MTRR_PHYS_MASK(2), |
| 30 | MTRR_PHYS_BASE(3), |
| 31 | MTRR_PHYS_MASK(3), |
| 32 | MTRR_PHYS_BASE(4), |
| 33 | MTRR_PHYS_MASK(4), |
| 34 | MTRR_PHYS_BASE(5), |
| 35 | MTRR_PHYS_MASK(5), |
| 36 | MTRR_PHYS_BASE(6), |
| 37 | MTRR_PHYS_MASK(6), |
| 38 | MTRR_PHYS_BASE(7), |
| 39 | MTRR_PHYS_MASK(7), |
| 40 | SYSCFG_MSR, |
| 41 | TOP_MEM, |
| 42 | TOP_MEM2, |
| 43 | }; |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 44 | |
| 45 | void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) |
| 46 | { |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 47 | msr_t syscfg_msr; |
| 48 | msr_t *mtrr_save = (msr_t *)mtrr_store; |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 49 | |
| 50 | /* Enable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 51 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 52 | syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 53 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 54 | |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 55 | for (int i = 0; i < ARRAY_SIZE(msr_backup); i++) |
| 56 | *mtrr_save++ = rdmsr(msr_backup[i]); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 57 | |
| 58 | /* Disable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 59 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 60 | syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 61 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 62 | |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 63 | *mtrr_store_size = sizeof(msr_t) * ARRAY_SIZE(msr_backup); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 64 | } |
| 65 | |
| 66 | void restore_mtrr(void) |
| 67 | { |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 68 | msr_t syscfg_msr; |
| 69 | msr_t *mtrr_save = (msr_t *)OemS3Saved_MTRR_Storage(); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 70 | |
| 71 | /* Enable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 72 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 73 | syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 74 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 75 | |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 76 | for (int i = 0; i < ARRAY_SIZE(msr_backup); i++) |
| 77 | wrmsr(msr_backup[i], *mtrr_save++); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 78 | |
| 79 | /* Disable access to AMD RdDram and WrDram extension bits */ |
Arthur Heymans | df3d97e | 2020-08-07 21:55:20 +0200 | [diff] [blame^] | 80 | syscfg_msr = rdmsr(SYSCFG_MSR); |
| 81 | syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 82 | wrmsr(SYSCFG_MSR, syscfg_msr); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 83 | } |