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Angel Pons8a3453f2020-04-02 23:48:19 +02001/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +02002
3#include <stdint.h>
4#include <cpu/x86/msr.h>
5#include <cpu/x86/mtrr.h>
6#include <cpu/amd/mtrr.h>
7#include <cpu/x86/cache.h>
8#include <string.h>
Kyösti Mälkkid4955f02017-09-08 07:14:17 +03009#include <northbridge/amd/agesa/agesa_helper.h>
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020010
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020011/* TODO: Do we want MTRR_DEF_TYPE_MSR too? */
12static const uint32_t msr_backup[] = {
13 MTRR_FIX_64K_00000,
14 MTRR_FIX_16K_80000,
15 MTRR_FIX_16K_A0000,
16 MTRR_FIX_4K_C0000,
17 MTRR_FIX_4K_C8000,
18 MTRR_FIX_4K_D0000,
19 MTRR_FIX_4K_D8000,
20 MTRR_FIX_4K_E0000,
21 MTRR_FIX_4K_E8000,
22 MTRR_FIX_4K_F0000,
23 MTRR_FIX_4K_F8000,
24 MTRR_PHYS_BASE(0),
25 MTRR_PHYS_MASK(0),
26 MTRR_PHYS_BASE(1),
27 MTRR_PHYS_MASK(1),
28 MTRR_PHYS_BASE(2),
29 MTRR_PHYS_MASK(2),
30 MTRR_PHYS_BASE(3),
31 MTRR_PHYS_MASK(3),
32 MTRR_PHYS_BASE(4),
33 MTRR_PHYS_MASK(4),
34 MTRR_PHYS_BASE(5),
35 MTRR_PHYS_MASK(5),
36 MTRR_PHYS_BASE(6),
37 MTRR_PHYS_MASK(6),
38 MTRR_PHYS_BASE(7),
39 MTRR_PHYS_MASK(7),
40 SYSCFG_MSR,
41 TOP_MEM,
42 TOP_MEM2,
43};
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020044
45void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size)
46{
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020047 msr_t syscfg_msr;
48 msr_t *mtrr_save = (msr_t *)mtrr_store;
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020049
50 /* Enable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020051 syscfg_msr = rdmsr(SYSCFG_MSR);
52 syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
53 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020054
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020055 for (int i = 0; i < ARRAY_SIZE(msr_backup); i++)
56 *mtrr_save++ = rdmsr(msr_backup[i]);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020057
58 /* Disable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020059 syscfg_msr = rdmsr(SYSCFG_MSR);
60 syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
61 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020062
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020063 *mtrr_store_size = sizeof(msr_t) * ARRAY_SIZE(msr_backup);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020064}
65
66void restore_mtrr(void)
67{
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020068 msr_t syscfg_msr;
69 msr_t *mtrr_save = (msr_t *)OemS3Saved_MTRR_Storage();
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020070
71 /* Enable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020072 syscfg_msr = rdmsr(SYSCFG_MSR);
73 syscfg_msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
74 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020075
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020076 for (int i = 0; i < ARRAY_SIZE(msr_backup); i++)
77 wrmsr(msr_backup[i], *mtrr_save++);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020078
79 /* Disable access to AMD RdDram and WrDram extension bits */
Arthur Heymansdf3d97e2020-08-07 21:55:20 +020080 syscfg_msr = rdmsr(SYSCFG_MSR);
81 syscfg_msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
82 wrmsr(SYSCFG_MSR, syscfg_msr);
Kyösti Mälkki5fdb95e2015-01-01 17:51:51 +020083}