Angel Pons | 8a3453f | 2020-04-02 23:48:19 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 2 | |
| 3 | #include <stdint.h> |
| 4 | #include <cpu/x86/msr.h> |
| 5 | #include <cpu/x86/mtrr.h> |
| 6 | #include <cpu/amd/mtrr.h> |
| 7 | #include <cpu/x86/cache.h> |
| 8 | #include <string.h> |
Kyösti Mälkki | d4955f0 | 2017-09-08 07:14:17 +0300 | [diff] [blame] | 9 | #include <northbridge/amd/agesa/agesa_helper.h> |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 10 | |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 11 | static void write_mtrr(u8 **p_nvram_pos, unsigned int idx) |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 12 | { |
| 13 | msr_t msr_data; |
| 14 | msr_data = rdmsr(idx); |
| 15 | |
| 16 | memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); |
| 17 | *p_nvram_pos += sizeof(msr_data); |
| 18 | } |
| 19 | |
| 20 | void backup_mtrr(void *mtrr_store, u32 *mtrr_store_size) |
| 21 | { |
| 22 | u8 *nvram_pos = mtrr_store; |
| 23 | msr_t msr_data; |
| 24 | u32 i; |
| 25 | |
| 26 | /* Enable access to AMD RdDram and WrDram extension bits */ |
| 27 | msr_data = rdmsr(SYSCFG_MSR); |
| 28 | msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 29 | wrmsr(SYSCFG_MSR, msr_data); |
| 30 | |
| 31 | /* Fixed MTRRs */ |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 32 | write_mtrr(&nvram_pos, MTRR_FIX_64K_00000); |
| 33 | write_mtrr(&nvram_pos, MTRR_FIX_16K_80000); |
| 34 | write_mtrr(&nvram_pos, MTRR_FIX_16K_A0000); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 35 | |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 36 | for (i = MTRR_FIX_4K_C0000; i <= MTRR_FIX_4K_F8000; i++) |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 37 | write_mtrr(&nvram_pos, i); |
| 38 | |
| 39 | /* Disable access to AMD RdDram and WrDram extension bits */ |
| 40 | msr_data = rdmsr(SYSCFG_MSR); |
| 41 | msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 42 | wrmsr(SYSCFG_MSR, msr_data); |
| 43 | |
| 44 | /* Variable MTRRs */ |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 45 | for (i = MTRR_PHYS_BASE(0); i < MTRR_PHYS_BASE(8); i++) |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 46 | write_mtrr(&nvram_pos, i); |
| 47 | |
| 48 | /* SYSCFG_MSR */ |
| 49 | write_mtrr(&nvram_pos, SYSCFG_MSR); |
| 50 | /* TOM */ |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 51 | write_mtrr(&nvram_pos, TOP_MEM); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 52 | /* TOM2 */ |
Elyes HAOUAS | 8a64370 | 2018-10-23 17:10:27 +0200 | [diff] [blame] | 53 | write_mtrr(&nvram_pos, TOP_MEM2); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 54 | |
| 55 | *mtrr_store_size = nvram_pos - (u8*) mtrr_store; |
| 56 | } |
| 57 | |
| 58 | void restore_mtrr(void) |
| 59 | { |
| 60 | volatile u32 *msrPtr = (u32 *) OemS3Saved_MTRR_Storage(); |
| 61 | u32 msr; |
| 62 | msr_t msr_data; |
| 63 | |
| 64 | if (!msrPtr) |
| 65 | return; |
| 66 | |
| 67 | disable_cache(); |
| 68 | |
| 69 | /* Enable access to AMD RdDram and WrDram extension bits */ |
| 70 | msr_data = rdmsr(SYSCFG_MSR); |
| 71 | msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 72 | wrmsr(SYSCFG_MSR, msr_data); |
| 73 | |
| 74 | /* Now restore the Fixed MTRRs */ |
| 75 | msr_data.lo = *msrPtr; |
| 76 | msrPtr ++; |
| 77 | msr_data.hi = *msrPtr; |
| 78 | msrPtr ++; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 79 | wrmsr(MTRR_FIX_64K_00000, msr_data); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 80 | |
| 81 | msr_data.lo = *msrPtr; |
| 82 | msrPtr ++; |
| 83 | msr_data.hi = *msrPtr; |
| 84 | msrPtr ++; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 85 | wrmsr(MTRR_FIX_16K_80000, msr_data); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 86 | |
| 87 | msr_data.lo = *msrPtr; |
| 88 | msrPtr ++; |
| 89 | msr_data.hi = *msrPtr; |
| 90 | msrPtr ++; |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 91 | wrmsr(MTRR_FIX_16K_A0000, msr_data); |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 92 | |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 93 | for (msr = MTRR_FIX_4K_C0000; msr <= MTRR_FIX_4K_F8000; msr++) { |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 94 | msr_data.lo = *msrPtr; |
| 95 | msrPtr ++; |
| 96 | msr_data.hi = *msrPtr; |
| 97 | msrPtr ++; |
| 98 | wrmsr(msr, msr_data); |
| 99 | } |
| 100 | |
| 101 | /* Disable access to AMD RdDram and WrDram extension bits */ |
| 102 | msr_data = rdmsr(SYSCFG_MSR); |
| 103 | msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 104 | wrmsr(SYSCFG_MSR, msr_data); |
| 105 | |
| 106 | /* Restore the Variable MTRRs */ |
Elyes HAOUAS | d50cf23 | 2018-10-17 20:18:17 +0200 | [diff] [blame] | 107 | for (msr = MTRR_PHYS_BASE(0); msr <= MTRR_PHYS_MASK(7); msr++) { |
Kyösti Mälkki | 5fdb95e | 2015-01-01 17:51:51 +0200 | [diff] [blame] | 108 | msr_data.lo = *msrPtr; |
| 109 | msrPtr ++; |
| 110 | msr_data.hi = *msrPtr; |
| 111 | msrPtr ++; |
| 112 | wrmsr(msr, msr_data); |
| 113 | } |
| 114 | |
| 115 | /* Restore SYSCFG MTRR */ |
| 116 | msr_data.lo = *msrPtr; |
| 117 | msrPtr ++; |
| 118 | msr_data.hi = *msrPtr; |
| 119 | msrPtr ++; |
| 120 | wrmsr(SYSCFG_MSR, msr_data); |
| 121 | } |