Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com> |
| 5 | * Copyright (C) 2007-2008 coresystems GmbH |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
Patrick Georgi | b890a12 | 2015-03-26 15:17:45 +0100 | [diff] [blame] | 18 | * Foundation, Inc. |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 19 | */ |
| 20 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 21 | #include <cpu/x86/mtrr.h> |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 22 | #include <cpu/x86/cache.h> |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 23 | #include <cpu/x86/post_code.h> |
| 24 | #include <cbmem.h> |
| 25 | |
| 26 | #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE |
| 27 | #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE |
| 28 | |
| 29 | /* Cache 4GB - MRC_SIZE_KB for MRC */ |
| 30 | #define CACHE_MRC_BYTES ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1) |
| 31 | #define CACHE_MRC_BASE (0xFFFFFFFF - CACHE_MRC_BYTES) |
| 32 | #define CACHE_MRC_MASK (~CACHE_MRC_BYTES) |
| 33 | |
Kyösti Mälkki | c7fb2ae | 2012-06-28 21:26:41 +0300 | [diff] [blame] | 34 | #define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 35 | |
| 36 | #define NoEvictMod_MSR 0x2e0 |
| 37 | |
| 38 | /* Save the BIST result. */ |
| 39 | movl %eax, %ebp |
| 40 | |
| 41 | cache_as_ram: |
| 42 | post_code(0x20) |
| 43 | |
| 44 | /* Send INIT IPI to all excluding ourself. */ |
| 45 | movl $0x000C4500, %eax |
| 46 | movl $0xFEE00300, %esi |
| 47 | movl %eax, (%esi) |
| 48 | |
| 49 | /* All CPUs need to be in Wait for SIPI state */ |
| 50 | wait_for_sipi: |
| 51 | movl (%esi), %eax |
| 52 | bt $12, %eax |
| 53 | jc wait_for_sipi |
| 54 | |
| 55 | post_code(0x21) |
| 56 | /* Zero out all fixed range and variable range MTRRs. */ |
| 57 | movl $mtrr_table, %esi |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 58 | movl $((mtrr_table_end - mtrr_table) >> 1), %edi |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 59 | xorl %eax, %eax |
| 60 | xorl %edx, %edx |
| 61 | clear_mtrrs: |
| 62 | movw (%esi), %bx |
| 63 | movzx %bx, %ecx |
| 64 | wrmsr |
| 65 | add $2, %esi |
| 66 | dec %edi |
| 67 | jnz clear_mtrrs |
| 68 | |
| 69 | post_code(0x22) |
| 70 | /* Configure the default memory type to uncacheable. */ |
| 71 | movl $MTRRdefType_MSR, %ecx |
| 72 | rdmsr |
| 73 | andl $(~0x00000cff), %eax |
| 74 | wrmsr |
| 75 | |
| 76 | post_code(0x23) |
| 77 | /* Set Cache-as-RAM base address. */ |
| 78 | movl $(MTRRphysBase_MSR(0)), %ecx |
| 79 | movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax |
| 80 | xorl %edx, %edx |
| 81 | wrmsr |
| 82 | |
| 83 | post_code(0x24) |
| 84 | /* Set Cache-as-RAM mask. */ |
| 85 | movl $(MTRRphysMask_MSR(0)), %ecx |
| 86 | movl $(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax |
| 87 | movl $CPU_PHYSMASK_HI, %edx |
| 88 | wrmsr |
| 89 | |
| 90 | post_code(0x25) |
| 91 | |
| 92 | /* Enable MTRR. */ |
| 93 | movl $MTRRdefType_MSR, %ecx |
| 94 | rdmsr |
| 95 | orl $MTRRdefTypeEn, %eax |
| 96 | wrmsr |
| 97 | |
| 98 | /* Enable cache (CR0.CD = 0, CR0.NW = 0). */ |
| 99 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 100 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 101 | invd |
| 102 | movl %eax, %cr0 |
| 103 | |
| 104 | /* enable the 'no eviction' mode */ |
| 105 | movl $NoEvictMod_MSR, %ecx |
| 106 | rdmsr |
| 107 | orl $1, %eax |
| 108 | andl $~2, %eax |
| 109 | wrmsr |
| 110 | |
| 111 | /* Clear the cache memory region. This will also fill up the cache */ |
| 112 | movl $CACHE_AS_RAM_BASE, %esi |
| 113 | movl %esi, %edi |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 114 | movl $(CACHE_AS_RAM_SIZE >> 2), %ecx |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 115 | // movl $0x23322332, %eax |
| 116 | xorl %eax, %eax |
| 117 | rep stosl |
| 118 | |
| 119 | /* enable the 'no eviction run' state */ |
| 120 | movl $NoEvictMod_MSR, %ecx |
| 121 | rdmsr |
| 122 | orl $3, %eax |
| 123 | wrmsr |
| 124 | |
| 125 | post_code(0x26) |
| 126 | /* Enable Cache-as-RAM mode by disabling cache. */ |
| 127 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 128 | orl $CR0_CacheDisable, %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 129 | movl %eax, %cr0 |
| 130 | |
| 131 | /* Enable cache for our code in Flash because we do XIP here */ |
| 132 | movl $MTRRphysBase_MSR(1), %ecx |
| 133 | xorl %edx, %edx |
| 134 | /* |
| 135 | * IMPORTANT: The following calculation _must_ be done at runtime. See |
| 136 | * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html |
| 137 | */ |
| 138 | movl $copy_and_run, %eax |
| 139 | andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax |
| 140 | orl $MTRR_TYPE_WRPROT, %eax |
| 141 | wrmsr |
| 142 | |
| 143 | movl $MTRRphysMask_MSR(1), %ecx |
| 144 | movl $CPU_PHYSMASK_HI, %edx |
| 145 | movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax |
| 146 | wrmsr |
| 147 | |
| 148 | post_code(0x27) |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 149 | /* Enable caching for ram init code to run faster */ |
| 150 | movl $MTRRphysBase_MSR(2), %ecx |
| 151 | movl $(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax |
| 152 | xorl %edx, %edx |
| 153 | wrmsr |
| 154 | movl $MTRRphysMask_MSR(2), %ecx |
| 155 | movl $(CACHE_MRC_MASK | MTRRphysMaskValid), %eax |
| 156 | movl $CPU_PHYSMASK_HI, %edx |
| 157 | wrmsr |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 158 | |
| 159 | post_code(0x28) |
| 160 | /* Enable cache. */ |
| 161 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 162 | andl $(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 163 | movl %eax, %cr0 |
| 164 | |
| 165 | /* Set up the stack pointer below MRC variable space. */ |
| 166 | movl $(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \ |
| 167 | CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax |
| 168 | movl %eax, %esp |
| 169 | |
| 170 | /* Restore the BIST result. */ |
| 171 | movl %ebp, %eax |
| 172 | movl %esp, %ebp |
| 173 | pushl %eax |
| 174 | |
| 175 | before_romstage: |
| 176 | post_code(0x29) |
| 177 | /* Call romstage.c main function. */ |
| 178 | call main |
| 179 | |
| 180 | post_code(0x2f) |
| 181 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 182 | post_code(0x30) |
| 183 | |
| 184 | /* Disable cache. */ |
| 185 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 186 | orl $CR0_CacheDisable, %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 187 | movl %eax, %cr0 |
| 188 | |
| 189 | post_code(0x31) |
| 190 | |
| 191 | /* Disable MTRR. */ |
| 192 | movl $MTRRdefType_MSR, %ecx |
| 193 | rdmsr |
| 194 | andl $(~MTRRdefTypeEn), %eax |
| 195 | wrmsr |
| 196 | |
| 197 | post_code(0x31) |
| 198 | |
| 199 | /* Disable the no eviction run state */ |
| 200 | movl $NoEvictMod_MSR, %ecx |
| 201 | rdmsr |
| 202 | andl $~2, %eax |
| 203 | wrmsr |
| 204 | |
| 205 | invd |
| 206 | |
| 207 | /* Disable the no eviction mode */ |
| 208 | rdmsr |
| 209 | andl $~1, %eax |
| 210 | wrmsr |
| 211 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 212 | /* Clear MTRR that was used to cache MRC */ |
| 213 | xorl %eax, %eax |
| 214 | xorl %edx, %edx |
| 215 | movl $MTRRphysBase_MSR(2), %ecx |
| 216 | wrmsr |
| 217 | movl $MTRRphysMask_MSR(2), %ecx |
| 218 | wrmsr |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 219 | |
| 220 | post_code(0x33) |
| 221 | |
| 222 | /* Enable cache. */ |
| 223 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 224 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 225 | movl %eax, %cr0 |
| 226 | |
| 227 | post_code(0x36) |
| 228 | |
| 229 | /* Disable cache. */ |
| 230 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 231 | orl $CR0_CacheDisable, %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 232 | movl %eax, %cr0 |
| 233 | |
| 234 | post_code(0x38) |
| 235 | |
| 236 | /* Enable Write Back and Speculative Reads for the first MB |
Furquan Shaikh | 20f25dd | 2014-04-22 10:41:05 -0700 | [diff] [blame] | 237 | * and ramstage. |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 238 | */ |
| 239 | movl $MTRRphysBase_MSR(0), %ecx |
| 240 | movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax |
| 241 | xorl %edx, %edx |
| 242 | wrmsr |
| 243 | movl $MTRRphysMask_MSR(0), %ecx |
| 244 | movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax |
| 245 | movl $CPU_PHYSMASK_HI, %edx // 36bit address space |
| 246 | wrmsr |
| 247 | |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 248 | #if CACHE_ROM_SIZE |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 249 | /* Enable Caching and speculative Reads for the |
| 250 | * complete ROM now that we actually have RAM. |
| 251 | */ |
| 252 | movl $MTRRphysBase_MSR(1), %ecx |
Kyösti Mälkki | 5458b9d | 2012-06-30 11:41:08 +0300 | [diff] [blame] | 253 | movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 254 | xorl %edx, %edx |
| 255 | wrmsr |
| 256 | movl $MTRRphysMask_MSR(1), %ecx |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 257 | movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 258 | movl $CPU_PHYSMASK_HI, %edx |
| 259 | wrmsr |
Kyösti Mälkki | 5458b9d | 2012-06-30 11:41:08 +0300 | [diff] [blame] | 260 | #endif |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 261 | |
| 262 | post_code(0x39) |
| 263 | |
| 264 | /* And enable cache again after setting MTRRs. */ |
| 265 | movl %cr0, %eax |
Patrick Georgi | 05e740f | 2012-03-31 12:52:21 +0200 | [diff] [blame] | 266 | andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 267 | movl %eax, %cr0 |
| 268 | |
| 269 | post_code(0x3a) |
| 270 | |
| 271 | /* Enable MTRR. */ |
| 272 | movl $MTRRdefType_MSR, %ecx |
| 273 | rdmsr |
| 274 | orl $MTRRdefTypeEn, %eax |
| 275 | wrmsr |
| 276 | |
| 277 | post_code(0x3b) |
| 278 | |
| 279 | /* Invalidate the cache again. */ |
| 280 | invd |
| 281 | |
| 282 | post_code(0x3c) |
| 283 | |
| 284 | #if CONFIG_HAVE_ACPI_RESUME |
| 285 | movl CBMEM_BOOT_MODE, %eax |
| 286 | cmpl $0x2, %eax // Resume? |
| 287 | jne __acpi_resume_backup_done |
| 288 | |
| 289 | /* copy 1MB - 64K to high tables ram_base to prevent memory corruption |
| 290 | * through stage 2. We could keep stuff like stack and heap in high |
| 291 | * tables memory completely, but that's a wonderful clean up task for |
| 292 | * another day. |
| 293 | */ |
| 294 | cld |
| 295 | movl $CONFIG_RAMBASE, %esi |
| 296 | movl CBMEM_RESUME_BACKUP, %edi |
Stefan Reinauer | 4a45ec4 | 2015-07-07 00:54:05 +0200 | [diff] [blame] | 297 | movl $HIGH_MEMORY_SAVE >> 2, %ecx |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 298 | rep movsl |
| 299 | |
| 300 | __acpi_resume_backup_done: |
| 301 | #endif |
| 302 | |
| 303 | post_code(0x3d) |
| 304 | |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 305 | __main: |
| 306 | post_code(POST_PREPARE_RAMSTAGE) |
| 307 | cld /* Clear direction flag. */ |
| 308 | |
Kyösti Mälkki | 1729cd8 | 2014-10-16 12:47:25 +0300 | [diff] [blame] | 309 | movl $CONFIG_RAMTOP, %esp |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 310 | movl %esp, %ebp |
Stefan Reinauer | 5c55463 | 2012-04-04 00:09:50 +0200 | [diff] [blame] | 311 | call copy_and_run |
| 312 | |
| 313 | .Lhlt: |
| 314 | post_code(POST_DEAD_CODE) |
| 315 | hlt |
| 316 | jmp .Lhlt |
| 317 | |
| 318 | mtrr_table: |
| 319 | /* Fixed MTRRs */ |
| 320 | .word 0x250, 0x258, 0x259 |
| 321 | .word 0x268, 0x269, 0x26A |
| 322 | .word 0x26B, 0x26C, 0x26D |
| 323 | .word 0x26E, 0x26F |
| 324 | /* Variable MTRRs */ |
| 325 | .word 0x200, 0x201, 0x202, 0x203 |
| 326 | .word 0x204, 0x205, 0x206, 0x207 |
| 327 | .word 0x208, 0x209, 0x20A, 0x20B |
| 328 | .word 0x20C, 0x20D, 0x20E, 0x20F |
| 329 | .word 0x210, 0x211, 0x212, 0x213 |
| 330 | mtrr_table_end: |