Subrata Banik | 76806c3 | 2022-01-03 17:33:35 +0000 | [diff] [blame] | 1 | config DISABLE_HECI1_AT_PRE_BOOT |
| 2 | bool "Disable HECI1 at the end of boot" |
| 3 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 4 | default n |
| 5 | help |
| 6 | This config decides the state of HECI1(CSE) device at the end of boot. |
| 7 | Mainboard users to select this config to make HECI1 `function disable` |
| 8 | prior to handing off to payload. |
| 9 | |
Subrata Banik | 526cc3e | 2022-01-31 21:55:51 +0530 | [diff] [blame] | 10 | config MAX_HECI_DEVICES |
| 11 | int |
| 12 | default 6 |
| 13 | |
| 14 | config SOC_INTEL_COMMON_BLOCK_CSE |
| 15 | bool |
| 16 | default n |
| 17 | help |
| 18 | Driver for communication with Converged Security Engine (CSE) |
| 19 | over Host Embedded Controller Interface (HECI) |
| 20 | |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 21 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_SBI |
Subrata Banik | 7e89984 | 2018-05-17 18:28:26 +0530 | [diff] [blame] | 22 | bool |
| 23 | default y if HECI_DISABLE_USING_SMM |
| 24 | select SOC_INTEL_COMMON_BLOCK_P2SB |
| 25 | help |
Subrata Banik | 32e0673 | 2022-01-28 02:05:15 +0530 | [diff] [blame] | 26 | Use this config to allow common CSE block to make HECI1 function disable |
| 27 | in the SMM mode. From CNL PCH onwards,`HECI1` disabling can only be done |
| 28 | using the non-posted sideband write after FSP-S sets the postboot_sai |
| 29 | attribute. |
| 30 | |
| 31 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC |
| 32 | bool |
| 33 | default n |
| 34 | select SOC_INTEL_COMMON_BLOCK_PMC |
| 35 | help |
| 36 | Use this config to allow common CSE block to make HECI1 function disable |
| 37 | using PMC IPC command `0xA9`. From TGL PCH onwards, disabling heci1 |
| 38 | device using PMC IPC doesn't required to run the operation in SMM. |
| 39 | |
| 40 | config SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR |
| 41 | bool |
| 42 | default n |
| 43 | select SOC_INTEL_COMMON_BLOCK_PCR |
| 44 | help |
| 45 | Use this config for SoC platform prior to CNL PCH (with postboot_sai implemented) |
| 46 | to make `HECI1` device disable using private configuration register (PCR) write. |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 47 | |
Subrata Banik | 2172a63 | 2023-06-22 01:00:06 +0530 | [diff] [blame] | 48 | config SOC_INTEL_STORE_CSE_FW_VERSION |
| 49 | bool |
Subrata Banik | c8a0417 | 2023-08-13 13:17:22 +0000 | [diff] [blame] | 50 | default y |
Subrata Banik | 2172a63 | 2023-06-22 01:00:06 +0530 | [diff] [blame] | 51 | depends on SOC_INTEL_CSE_LITE_SKU |
| 52 | help |
| 53 | This configuration option stores CSE RW FW version in CBMEM area. |
| 54 | This information can be used to identify if the CSE firmware update is successful |
| 55 | by comparing the currently running CSE RW firmware version against CSE version |
| 56 | belongs to the CONFIG_SOC_INTEL_CSE_RW_VERSION (decided statically while |
| 57 | building the AP FW image). |
| 58 | |
| 59 | The way to retrieve the CSE firmware version is by sending the HECI command to |
| 60 | read the CSE Boot Partition (BP) info. The cost of sending HECI command to read |
| 61 | the CSE FW version is between 7ms-20ms (depending on the SoC architecture) hence, |
| 62 | ensure this feature is platform specific and only enabled for the platform |
| 63 | that would like to store the CSE version into the CBMEM. |
| 64 | |
Dinesh Gehlot | 91da19c | 2023-05-07 13:47:49 +0000 | [diff] [blame] | 65 | config SOC_INTEL_CSE_FW_PARTITION_CMOS_OFFSET |
| 66 | int |
| 67 | default 68 |
| 68 | depends on SOC_INTEL_CSE_LITE_SKU |
| 69 | help |
| 70 | This configuration option stores the starting offset of cse fw partition versions in |
| 71 | CMOS memory. The offset should be byte aligned and must leave enough memory to store |
| 72 | required firmware partition versions. |
| 73 | |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 74 | config SOC_INTEL_STORE_ISH_FW_VERSION |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 75 | bool |
| 76 | default n |
| 77 | depends on DRIVERS_INTEL_ISH |
| 78 | help |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 79 | This configuration option stores ISH version in CBMEM area. |
| 80 | This information can be used to identify the currently running ISH firmware |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 81 | version. |
| 82 | |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 83 | ISH BUP is sitting inside the CSE firmware partition. The way to retrieve the |
| 84 | ISH version is by sending the HECI command to read the CSE FPT. The cost of sending |
| 85 | HECI command to read the CSE FPT is significant (~200ms) hence, the idea is to |
| 86 | read the CSE RW version on every cold reset (to cover the CSE update scenarios) |
| 87 | and store into CBMEM to avoid the cost of resending the HECI command in all |
| 88 | consecutive warm boots. |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 89 | |
Subrata Banik | 272ce9a | 2023-06-13 00:44:44 +0530 | [diff] [blame] | 90 | Later boot stages can just read the CBMEM ID to retrieve the ISH version. |
Subrata Banik | fc313d6 | 2023-04-14 01:31:29 +0530 | [diff] [blame] | 91 | |
| 92 | Additionally, ensure this feature is platform specific hence, only enabled |
| 93 | for the platform that would like to store the ISH version into the CBMEM and |
| 94 | parse to perform some additional work. |
| 95 | |
MAULIK V VAGHELA | 61b8f89 | 2021-12-17 17:55:22 +0530 | [diff] [blame] | 96 | config SOC_INTEL_CSE_SEND_EOP_EARLY |
Michał Kopeć | 9c4ae91 | 2022-10-29 18:00:18 +0200 | [diff] [blame] | 97 | bool "CSE send EOP early" |
MAULIK V VAGHELA | 61b8f89 | 2021-12-17 17:55:22 +0530 | [diff] [blame] | 98 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 99 | help |
| 100 | Use this config to send End Of Post (EOP) earlier through SoC code in order to |
| 101 | reduce time required to send EOP and getting CSE response. |
| 102 | In later stages, CSE might be busy and might require more time to process EOP command. |
| 103 | SoC can use this Kconfig to send EOP earlier by itself. |
| 104 | |
Subrata Banik | bed82b0 | 2022-11-24 21:02:00 +0530 | [diff] [blame] | 105 | config SOC_INTEL_CSE_SEND_EOP_LATE |
| 106 | bool |
| 107 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 108 | help |
| 109 | Use this config to send End Of Post (EOP) late (even after CSE `final` operation) |
| 110 | using boot state either `BS_PAYLOAD_BOOT` or `BS_PAYLOAD_LOAD` from common code |
| 111 | in order to reduce time required to send EOP and getting CSE response. |
| 112 | It has been observed that CSE might be busy and might require more time to |
| 113 | process the EOP command. |
| 114 | SoC can use this Kconfig to send EOP later by itself. |
| 115 | Starting with Jasper Lake, coreboot sends EOP before loading payload hence, this |
| 116 | config is applicable for those platforms. |
| 117 | |
Jeremy Compostella | 1d79188 | 2023-03-13 13:59:08 -0700 | [diff] [blame] | 118 | config SOC_INTEL_CSE_SEND_EOP_ASYNC |
| 119 | bool |
| 120 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 121 | depends on !SOC_INTEL_CSE_SEND_EOP_LATE |
| 122 | depends on !SOC_INTEL_CSE_SEND_EOP_EARLY |
| 123 | help |
| 124 | Use this config to handle End Of Post (EOP) completion |
| 125 | asynchronously. The EOP command is sent first and the result |
| 126 | is checked later leaving time to CSE to complete the |
| 127 | operation while coreboot perform other activities. |
| 128 | Performing EOP asynchronously reduces the time spent |
| 129 | actively waiting for command completion which can have a |
| 130 | significant impact on boot time. |
| 131 | |
| 132 | Using this asynchronous approach comes with the limitation |
| 133 | that no HECI command should be sent between the time the EOP |
| 134 | request is posted (at CSE .final device operation) and the |
| 135 | time coreboot check for its completion (BS_PAYLOAD_LOAD). |
| 136 | |
Kapil Porwal | e1b5996 | 2023-04-26 00:33:53 +0530 | [diff] [blame] | 137 | config SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD |
| 138 | bool |
| 139 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 140 | depends on !SOC_INTEL_CSE_SEND_EOP_LATE |
| 141 | depends on !SOC_INTEL_CSE_SEND_EOP_EARLY |
| 142 | depends on !SOC_INTEL_CSE_SEND_EOP_ASYNC |
| 143 | depends on !DISABLE_HECI1_AT_PRE_BOOT |
| 144 | help |
| 145 | Use this config to specify that the payload will send the End Of Post (EOP) instead |
| 146 | of coreboot. |
| 147 | |
| 148 | In this case, the HECI interface needs to stay visible and the payload must support |
| 149 | sending commands to CSE. |
| 150 | |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 151 | config SOC_INTEL_CSE_LITE_SKU |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 152 | bool |
| 153 | default n |
Sridhar Siricilla | f87ff33 | 2019-09-12 17:18:20 +0530 | [diff] [blame] | 154 | help |
Sridhar Siricilla | 99dbca3 | 2020-05-12 21:05:04 +0530 | [diff] [blame] | 155 | Enables CSE Lite SKU |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 156 | |
Krishna Prasad Bhat | 9ab161d | 2023-07-18 14:25:37 +0530 | [diff] [blame] | 157 | config SOC_INTEL_CSE_LITE_PSR |
| 158 | bool |
| 159 | default n |
| 160 | depends on SOC_INTEL_CSE_LITE_SKU |
Krishna Prasad Bhat | d2bc30f | 2023-09-22 00:28:50 +0530 | [diff] [blame] | 161 | select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE |
Krishna Prasad Bhat | 9ab161d | 2023-07-18 14:25:37 +0530 | [diff] [blame] | 162 | help |
| 163 | Select this config if Platform Service Record(PSR) is supported by the platform. This |
| 164 | config is applicable only for Lite SKU, where PSR data backup is required prior to a |
Krishna Prasad Bhat | d2bc30f | 2023-09-22 00:28:50 +0530 | [diff] [blame] | 165 | CSE firmware downgrade during which CSE data is cleared. PSR services in CSE FW is |
| 166 | enabled only post DRAM init and the command to backup PSR data is also supported only |
| 167 | post DRAM init. Hence platform that selects PSR would need to perform CSE firmware sync |
| 168 | in ramstage. |
Krishna Prasad Bhat | 9ab161d | 2023-07-18 14:25:37 +0530 | [diff] [blame] | 169 | |
Johnny Lin | a3e68c9 | 2022-08-09 15:36:30 +0800 | [diff] [blame] | 170 | config SOC_INTEL_CSE_SERVER_SKU |
| 171 | bool |
| 172 | default n |
| 173 | help |
| 174 | Enables CSE Server SKU |
| 175 | |
V Sowmya | f990552 | 2020-11-12 20:19:04 +0530 | [diff] [blame] | 176 | config SOC_INTEL_CSE_RW_UPDATE |
| 177 | bool "Enable the CSE RW Update Feature" |
| 178 | default n |
| 179 | depends on SOC_INTEL_CSE_LITE_SKU |
| 180 | help |
| 181 | This config will enable CSE RW firmware update feature and also will be used ensure |
| 182 | all the required configs are provided by mainboard. |
| 183 | |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 184 | config SOC_INTEL_CSE_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 185 | string "Name of CSE Region in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 186 | default "SI_ME" |
| 187 | help |
| 188 | Name of CSE region in FMAP |
| 189 | |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 190 | config SOC_INTEL_CSE_RW_A_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 191 | string "Location of CSE RW A in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 192 | default "ME_RW_A" |
| 193 | help |
| 194 | Name of CSE RW A region in FMAP |
| 195 | |
| 196 | config SOC_INTEL_CSE_RW_B_FMAP_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 197 | string "Location of CSE RW B in FMAP" if SOC_INTEL_CSE_RW_UPDATE |
Sridhar Siricilla | 361e364 | 2020-10-18 20:14:07 +0530 | [diff] [blame] | 198 | default "ME_RW_B" |
| 199 | help |
| 200 | Name of CSE RW B region in FMAP |
| 201 | |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 202 | config SOC_INTEL_CSE_RW_CBFS_NAME |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 203 | string "CBFS entry name for CSE RW blob" if SOC_INTEL_CSE_RW_UPDATE |
Rizwan Qureshi | ec32109 | 2019-09-06 20:28:43 +0530 | [diff] [blame] | 204 | default "me_rw" |
| 205 | help |
| 206 | CBFS entry name for Intel CSE CBFS RW blob |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 207 | |
Furquan Shaikh | d2da870 | 2021-10-07 00:08:59 -0700 | [diff] [blame] | 208 | config SOC_INTEL_CSE_RW_HASH_CBFS_NAME |
| 209 | string "CBFS name for CSE RW hash file" if SOC_INTEL_CSE_RW_UPDATE |
| 210 | default "me_rw.hash" |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 211 | help |
Furquan Shaikh | d2da870 | 2021-10-07 00:08:59 -0700 | [diff] [blame] | 212 | CBFS name for Intel CSE CBFS RW hash file |
| 213 | |
| 214 | config SOC_INTEL_CSE_RW_VERSION_CBFS_NAME |
| 215 | string "CBFS name for CSE RW version file" if SOC_INTEL_CSE_RW_UPDATE |
| 216 | default "me_rw.version" |
| 217 | help |
| 218 | CBFS name for Intel CSE CBFS RW version file |
V Sowmya | 338b83c | 2020-11-11 07:04:13 +0530 | [diff] [blame] | 219 | |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 220 | config SOC_INTEL_CSE_RW_FILE |
Furquan Shaikh | 3f0d643 | 2021-10-09 00:08:56 -0700 | [diff] [blame] | 221 | string "Intel CSE CBFS RW path and filename" if SOC_INTEL_CSE_RW_UPDATE && !STITCH_ME_BIN |
Sridhar Siricilla | b2353a7 | 2019-09-13 16:32:00 +0530 | [diff] [blame] | 222 | default "" |
| 223 | help |
| 224 | Intel CSE CBFS RW blob path and file name |
V Sowmya | 187f06f | 2020-11-11 06:33:43 +0530 | [diff] [blame] | 225 | |
| 226 | config SOC_INTEL_CSE_RW_VERSION |
Sridhar Siricilla | 4c2890d | 2020-12-09 00:28:30 +0530 | [diff] [blame] | 227 | string "Intel CSE RW firmware version" if SOC_INTEL_CSE_RW_UPDATE |
V Sowmya | 187f06f | 2020-11-11 06:33:43 +0530 | [diff] [blame] | 228 | default "" |
| 229 | help |
| 230 | This config contains the Intel CSE RW version of the blob that is provided by |
| 231 | SOC_INTEL_CSE_RW_FILE config and the version must be set in the format |
| 232 | major.minor.hotfix.build (ex: 14.0.40.1209). |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 233 | |
| 234 | config SOC_INTEL_CSE_SET_EOP |
| 235 | bool |
| 236 | default n |
Tim Wawrzynczak | 9fdd2b2 | 2021-06-18 10:34:09 -0600 | [diff] [blame] | 237 | select PMC_IPC_ACPI_INTERFACE |
Tim Wawrzynczak | 064ca18 | 2021-06-17 12:40:13 -0600 | [diff] [blame] | 238 | help |
| 239 | This config ensures coreboot will send the CSE the End-of-POST message |
| 240 | just prior to loading the payload. This is a security feature so the |
| 241 | CSE will no longer respond to Pre-Boot commands. |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 242 | |
Krishna Prasad Bhat | 333edcc | 2021-11-26 06:52:27 +0530 | [diff] [blame] | 243 | config SOC_INTEL_CSE_SUB_PART_UPDATE |
| 244 | bool "Enable the CSE sub-partition update Feature" |
| 245 | default n |
| 246 | depends on SOC_INTEL_CSE_LITE_SKU |
| 247 | help |
| 248 | This config will enable CSE sub-partition firmware update feature and also will be used ensure |
| 249 | all the required configs are provided by mainboard. |
| 250 | |
| 251 | config SOC_INTEL_CSE_IOM_CBFS_NAME |
| 252 | string "CBFS name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 253 | default "cse_iom" |
| 254 | help |
| 255 | CBFS entry name for Intel CSE sub-partition IOM binary |
| 256 | |
| 257 | config SOC_INTEL_CSE_IOM_CBFS_FILE |
| 258 | string "Intel CBFS path and file name for CSE sub-partition IOM binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 259 | default "" |
| 260 | help |
| 261 | CBFS path and file name for Intel CSE sub-partition IOM binary |
| 262 | |
| 263 | config SOC_INTEL_CSE_NPHY_CBFS_NAME |
| 264 | string "CBFS name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 265 | default "cse_nphy" |
| 266 | help |
| 267 | CBFS entry name for Intel CSE sub-partition NPHY binary |
| 268 | |
| 269 | config SOC_INTEL_CSE_NPHY_CBFS_FILE |
| 270 | string "Intel CBFS path and file name for CSE sub-partition NPHY binary" if SOC_INTEL_CSE_SUB_PART_UPDATE |
| 271 | default "" |
| 272 | help |
| 273 | CBFS path and file name for Intel CSE sub-partition NPHY binary |
| 274 | |
Krishna Prasad Bhat | a67a92e | 2022-02-25 10:45:55 +0530 | [diff] [blame] | 275 | config SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |
| 276 | bool |
| 277 | default n |
| 278 | depends on SOC_INTEL_CSE_LITE_SKU |
Julius Werner | 6e303aa | 2023-05-25 18:26:32 -0700 | [diff] [blame] | 279 | select CBFS_ALLOW_UNVERIFIED_DECOMPRESSION if CBFS_VERIFICATION && !VBOOT_CBFS_INTEGRATION |
Krishna Prasad Bhat | a67a92e | 2022-02-25 10:45:55 +0530 | [diff] [blame] | 280 | help |
| 281 | Enable compression on Intel CSE CBFS RW blob |
| 282 | |
Bora Guvendik | 860672e | 2021-09-26 17:25:48 -0700 | [diff] [blame] | 283 | config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY |
| 284 | def_bool n |
| 285 | depends on SOC_INTEL_CSE_LITE_SKU |
| 286 | help |
| 287 | Mainboard user to select this Kconfig in order to capture pre-cpu |
| 288 | reset boot performance telemetry data. |
| 289 | |
Bora Guvendik | 9405049 | 2023-03-12 12:24:58 -0700 | [diff] [blame] | 290 | config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V1 |
| 291 | bool |
| 292 | select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY |
| 293 | help |
| 294 | This config will make mainboard use version 1 of the CSE timestamp |
| 295 | definitions, it can be used for Alder Lake and Raptor Lake (all SKUs). |
| 296 | |
| 297 | config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 |
| 298 | bool |
| 299 | select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY |
| 300 | help |
| 301 | This config will make mainboard use version 2 of the CSE timestamp |
| 302 | definitions, it can be used for Meteor Lake M/P. |
| 303 | |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 304 | config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE |
| 305 | bool |
Subrata Banik | 792ce81 | 2023-04-28 00:52:23 +0530 | [diff] [blame] | 306 | default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 307 | depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW |
| 308 | help |
| 309 | Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. |
| 310 | |
| 311 | config SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE |
| 312 | bool |
| 313 | default n |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 314 | help |
Anil Kumar | afb926a | 2023-04-26 11:31:20 -0700 | [diff] [blame] | 315 | Use this option if CSE RW update needs to be triggered during RAMSTAGE. |
Krishna Prasad Bhat | ddd66ed | 2022-06-23 22:14:28 +0530 | [diff] [blame] | 316 | |
Dinesh Gehlot | 73fcbf1 | 2023-02-20 06:18:23 +0000 | [diff] [blame] | 317 | config SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 318 | bool |
| 319 | depends on SOC_INTEL_COMMON_BLOCK_CSE |
| 320 | default n |
| 321 | help |
| 322 | This option config will allow SoC platform to use applicable ME specification. |
| 323 | The version based CSE measured ME specification data structures are defined at |
| 324 | common code. Enabling this option will use those CSE defined ME specification |
| 325 | for the SoC. User should select pertinent ME spec version along with this option. |
| 326 | |
| 327 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 |
| 328 | bool |
| 329 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 330 | help |
| 331 | This config will enable 'ME specification version 12'. It will ensure ME specific |
| 332 | declaration and uses of required data structures for Host firmware status registers. |
| 333 | |
| 334 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 |
| 335 | bool |
| 336 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 337 | help |
| 338 | This config will enable 'ME specification version 13'. It will ensure ME specific |
| 339 | declaration and uses of required data structures for Host firmware status registers. |
| 340 | |
| 341 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 |
| 342 | bool |
| 343 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 344 | help |
| 345 | This config will enable 'ME specification version 15'. It will ensure ME specific |
| 346 | declaration and uses of required data structures for Host firmware status registers. |
| 347 | |
| 348 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
| 349 | bool |
| 350 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 351 | help |
| 352 | This config will enable 'ME specification version 16'. It will ensure ME specific |
| 353 | declaration and uses of required data structures for Host firmware status registers. |
| 354 | |
| 355 | config SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
| 356 | bool |
| 357 | select SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 358 | help |
| 359 | This config will enable 'ME specification version 18'. It will ensure ME specific |
| 360 | declaration and uses of required data structures for Host firmware status registers. |
| 361 | |
| 362 | if SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 363 | |
| 364 | config ME_SPEC |
| 365 | int |
| 366 | default 12 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 |
| 367 | default 13 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 |
| 368 | default 15 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 |
| 369 | default 16 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_16 |
| 370 | default 18 if SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 |
| 371 | help |
| 372 | This config holds the ME spec version if defined. |
| 373 | |
| 374 | endif # SOC_INTEL_CSE_HAVE_SPEC_SUPPORT |
| 375 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 376 | if STITCH_ME_BIN |
| 377 | |
| 378 | config CSE_COMPONENTS_PATH |
| 379 | string "Path to directory containing all CSE input components to stitch" |
| 380 | default "3rdparty/blobs/mainboard/\$(CONFIG_MAINBOARD_DIR)/firmware" |
| 381 | help |
| 382 | This is the file path containing all the input CSE component files. |
| 383 | These will be used by cse_serger tool to stitch CSE image. |
| 384 | |
| 385 | config CSE_FPT_FILE |
| 386 | string "Name of CSE FPT file" |
| 387 | default "cse_fpt.bin" |
| 388 | help |
| 389 | This file is the CSE input binary as released by Intel in a CSE kit. |
| 390 | |
| 391 | config CSE_DATA_FILE |
| 392 | string "Name of CSE data file" |
| 393 | default "cse_data.bin" |
| 394 | help |
| 395 | This file is the CSE data binary typically generated by Intel FIT tool. |
| 396 | |
Reka Norman | 8d357b5 | 2023-08-07 06:49:32 +0000 | [diff] [blame] | 397 | config CSE_PMCP_FILE |
| 398 | string "Name of PMC file" |
| 399 | default "pmc.bin" |
| 400 | help |
| 401 | This file is the PMC input binary as released by Intel in a CSE kit. |
| 402 | |
| 403 | config CSE_IOMP_FILE |
| 404 | string "Name of IOM file" |
| 405 | default "iom.bin" |
| 406 | help |
| 407 | This file is the IOM input binary as released by Intel in a CSE kit. |
| 408 | |
| 409 | config CSE_TBTP_FILE |
| 410 | string "Name of TBT file" |
| 411 | default "tbt.bin" |
| 412 | help |
| 413 | This file is the TBT input binary as released by Intel in a CSE kit. |
| 414 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 415 | config CSE_NPHY_FILE |
| 416 | string "Name of NPHY file" |
| 417 | default "nphy.bin" |
| 418 | help |
| 419 | This file is the NPHY input binary as released by Intel in a CSE kit. |
| 420 | |
Reka Norman | 8d357b5 | 2023-08-07 06:49:32 +0000 | [diff] [blame] | 421 | config CSE_PCHC_FILE |
| 422 | string "Name of PCHC file" |
| 423 | default "pchc.bin" |
| 424 | help |
| 425 | This file is the PCHC input binary as released by Intel in a CSE kit. |
| 426 | |
| 427 | config CSE_IUNP_FILE |
| 428 | string "Name of IUNIT file" |
| 429 | default "iunit.bin" |
| 430 | help |
| 431 | This file is the PCHC input binary as released by Intel in a CSE kit. |
| 432 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 433 | config CSE_BPDT_VERSION |
| 434 | string |
| 435 | help |
| 436 | This config indicates the BPDT version used by CSE for a given SoC. |
| 437 | |
Reka Norman | 8d357b5 | 2023-08-07 06:49:32 +0000 | [diff] [blame] | 438 | config CSE_OEMP_FILE |
| 439 | string "Name of OEM Key Manifest file" |
| 440 | default "oem_km.bin" |
| 441 | help |
| 442 | OEM Key Manifest lists the public key hashes used for authenticating the |
| 443 | OEM created binaries to be loaded. This binary is generated by signing with |
| 444 | the key owned by trusted owner. |
| 445 | |
Furquan Shaikh | 6ef863c | 2021-10-01 11:39:48 -0700 | [diff] [blame] | 446 | endif |
Derek Huang | 2189640 | 2023-09-01 07:55:40 +0000 | [diff] [blame] | 447 | |
| 448 | config CSE_RESET_CLEAR_EC_AP_IDLE_FLAG |
| 449 | bool |
| 450 | default y if !SYSTEM_TYPE_LAPTOP |
| 451 | help |
| 452 | Select this if the variant is a Chromebox/base. This allows AP to direct EC |
| 453 | to clear AP_IDLE flag before triggering reset to make sure AP can boot up |
| 454 | after reset. |