Angel Pons | e67ab18 | 2020-04-04 18:51:11 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Huayang Duan | c2ef102 | 2018-09-26 14:24:02 +0800 | [diff] [blame] | 2 | |
Huayang Duan | 4d15d2f | 2018-09-26 21:23:53 +0800 | [diff] [blame] | 3 | #include <assert.h> |
Joel Kitching | 9a29228 | 2020-03-06 13:44:50 +0800 | [diff] [blame] | 4 | #include <bootmode.h> |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 5 | #include <cbfs.h> |
Huayang Duan | 4d15d2f | 2018-09-26 21:23:53 +0800 | [diff] [blame] | 6 | #include <console/console.h> |
Yu-Ping Wu | e67dce0 | 2019-10-14 16:56:50 +0800 | [diff] [blame] | 7 | #include <ip_checksum.h> |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 8 | #include <security/vboot/vboot_common.h> |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 9 | #include <soc/dramc_param.h> |
Huayang Duan | 4d15d2f | 2018-09-26 21:23:53 +0800 | [diff] [blame] | 10 | #include <soc/dramc_pi_api.h> |
Huayang Duan | c2ef102 | 2018-09-26 14:24:02 +0800 | [diff] [blame] | 11 | #include <soc/emi.h> |
Huayang Duan | e6ac20b | 2019-12-24 16:35:13 +0800 | [diff] [blame] | 12 | #include <soc/mt6358.h> |
Huayang Duan | 4d15d2f | 2018-09-26 21:23:53 +0800 | [diff] [blame] | 13 | #include <symbols.h> |
Huayang Duan | c2ef102 | 2018-09-26 14:24:02 +0800 | [diff] [blame] | 14 | |
Yu-Ping Wu | ffb5ea3 | 2019-10-07 15:55:57 +0800 | [diff] [blame] | 15 | static int mt_mem_test(void) |
Huayang Duan | c2ef102 | 2018-09-26 14:24:02 +0800 | [diff] [blame] | 16 | { |
Huayang Duan | 4d15d2f | 2018-09-26 21:23:53 +0800 | [diff] [blame] | 17 | u64 rank_size[RANK_MAX]; |
| 18 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 19 | if (CONFIG(MEMORY_TEST)) { |
Huayang Duan | 4d15d2f | 2018-09-26 21:23:53 +0800 | [diff] [blame] | 20 | size_t r; |
| 21 | u8 *addr = _dram; |
| 22 | |
| 23 | dramc_get_rank_size(rank_size); |
| 24 | |
| 25 | for (r = RANK_0; r < RANK_MAX; r++) { |
| 26 | int i; |
| 27 | |
| 28 | if (rank_size[r] == 0) |
| 29 | break; |
| 30 | |
| 31 | i = complex_mem_test(addr, 0x2000); |
| 32 | |
| 33 | printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s : %d\n", |
| 34 | (i == 0) ? "pass" : "fail", i); |
| 35 | |
Yu-Ping Wu | ffb5ea3 | 2019-10-07 15:55:57 +0800 | [diff] [blame] | 36 | if (i != 0) { |
Yu-Ping Wu | 31ec0c4 | 2019-10-09 16:11:47 +0800 | [diff] [blame] | 37 | printk(BIOS_ERR, "DRAM memory test failed\n"); |
Yu-Ping Wu | ffb5ea3 | 2019-10-07 15:55:57 +0800 | [diff] [blame] | 38 | return -1; |
| 39 | } |
Huayang Duan | 4d15d2f | 2018-09-26 21:23:53 +0800 | [diff] [blame] | 40 | |
| 41 | addr += rank_size[r]; |
| 42 | } |
| 43 | } |
Yu-Ping Wu | ffb5ea3 | 2019-10-07 15:55:57 +0800 | [diff] [blame] | 44 | |
| 45 | return 0; |
Huayang Duan | c2ef102 | 2018-09-26 14:24:02 +0800 | [diff] [blame] | 46 | } |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 47 | |
| 48 | static void dump_param_header(const struct dramc_param *dparam) |
| 49 | { |
| 50 | const struct dramc_param_header *header = &dparam->header; |
| 51 | |
| 52 | printk(BIOS_DEBUG, "header.status = %#x\n", header->status); |
| 53 | printk(BIOS_DEBUG, "header.magic = %#x (expected: %#x)\n", |
| 54 | header->magic, DRAMC_PARAM_HEADER_MAGIC); |
| 55 | printk(BIOS_DEBUG, "header.version = %#x (expected: %#x)\n", |
| 56 | header->version, DRAMC_PARAM_HEADER_VERSION); |
| 57 | printk(BIOS_DEBUG, "header.size = %#x (expected: %#lx)\n", |
| 58 | header->size, sizeof(*dparam)); |
| 59 | printk(BIOS_DEBUG, "header.config = %#x\n", header->config); |
| 60 | printk(BIOS_DEBUG, "header.flags = %#x\n", header->flags); |
| 61 | printk(BIOS_DEBUG, "header.checksum = %#x\n", header->checksum); |
| 62 | } |
| 63 | |
Yu-Ping Wu | e67dce0 | 2019-10-14 16:56:50 +0800 | [diff] [blame] | 64 | static u32 compute_checksum(const struct dramc_param *dparam) |
| 65 | { |
| 66 | return (u32)compute_ip_checksum(dparam->freq_params, |
| 67 | sizeof(dparam->freq_params)); |
| 68 | } |
| 69 | |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 70 | static int dram_run_fast_calibration(const struct dramc_param *dparam, |
| 71 | u16 config) |
| 72 | { |
| 73 | if (!is_valid_dramc_param(dparam)) { |
| 74 | printk(BIOS_WARNING, |
| 75 | "Invalid DRAM calibration data from flash\n"); |
| 76 | dump_param_header(dparam); |
| 77 | return -1; |
| 78 | } |
| 79 | |
Yu-Ping Wu | 31ec0c4 | 2019-10-09 16:11:47 +0800 | [diff] [blame] | 80 | if (dparam->header.config != config) { |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 81 | printk(BIOS_WARNING, |
| 82 | "Incompatible config for calibration data from flash " |
| 83 | "(expected: %#x, saved: %#x)\n", |
| 84 | config, dparam->header.config); |
| 85 | return -1; |
| 86 | } |
| 87 | |
Yu-Ping Wu | e67dce0 | 2019-10-14 16:56:50 +0800 | [diff] [blame] | 88 | const u32 checksum = compute_checksum(dparam); |
| 89 | if (dparam->header.checksum != checksum) { |
| 90 | printk(BIOS_ERR, |
| 91 | "Invalid DRAM calibration checksum from flash " |
| 92 | "(expected: %#x, saved: %#x)\n", |
| 93 | checksum, dparam->header.checksum); |
| 94 | return -1; |
| 95 | } |
| 96 | |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 97 | return 0; |
| 98 | } |
| 99 | |
Huayang Duan | 6e57b1c | 2020-07-23 13:53:39 +0800 | [diff] [blame] | 100 | static int dram_run_full_calibration(struct dramc_param *dparam, |
| 101 | u32 ddr_geometry, u16 config) |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 102 | { |
| 103 | initialize_dramc_param(dparam, config); |
| 104 | |
| 105 | /* Load and run the provided blob for full-calibration if available */ |
| 106 | struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram"); |
| 107 | |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 108 | if (cbfs_prog_stage_load(&dram)) |
| 109 | return -2; |
| 110 | |
Hung-Te Lin | beeab4e | 2019-10-15 17:49:24 +0800 | [diff] [blame] | 111 | dparam->do_putc = do_putchar; |
Huayang Duan | 6e57b1c | 2020-07-23 13:53:39 +0800 | [diff] [blame] | 112 | dparam->freq_params[0].ddr_geometry = ddr_geometry; |
| 113 | printk(BIOS_INFO, "ddr_geometry: %d, config: %#x\n", ddr_geometry, config); |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 114 | prog_set_entry(&dram, prog_entry(&dram), dparam); |
| 115 | prog_run(&dram); |
| 116 | |
| 117 | if (dparam->header.status != DRAMC_SUCCESS) { |
| 118 | printk(BIOS_ERR, "Full calibration failed: status = %d\n", |
| 119 | dparam->header.status); |
| 120 | return -3; |
| 121 | } |
| 122 | |
| 123 | if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) { |
| 124 | printk(BIOS_ERR, |
| 125 | "Full calibration executed without saving parameters. " |
| 126 | "Please ensure the blob is built properly.\n"); |
| 127 | return -4; |
| 128 | } |
| 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | static void set_source_to_flash(struct sdram_params *freq_params) |
| 134 | { |
| 135 | for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX; |
| 136 | shuffle++) |
| 137 | freq_params[shuffle].source = DRAMC_PARAM_SOURCE_FLASH; |
| 138 | } |
| 139 | |
| 140 | static void init_sdram_params(struct sdram_params *dst, |
| 141 | const struct sdram_params *src) |
| 142 | { |
| 143 | for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX; |
| 144 | shuffle++) |
| 145 | memcpy(&dst[shuffle], src, sizeof(*dst)); |
| 146 | } |
| 147 | |
Huayang Duan | e6ac20b | 2019-12-24 16:35:13 +0800 | [diff] [blame] | 148 | static void mt_mem_init_run(struct dramc_param_ops *dparam_ops) |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 149 | { |
| 150 | struct dramc_param *dparam = dparam_ops->param; |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 151 | |
| 152 | u16 config = 0; |
| 153 | if (CONFIG(MT8183_DRAM_EMCP)) |
| 154 | config |= DRAMC_CONFIG_EMCP; |
| 155 | |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 156 | const bool recovery_mode = vboot_recovery_mode_enabled(); |
| 157 | |
Yu-Ping Wu | 02d9071 | 2019-10-29 16:20:35 +0800 | [diff] [blame] | 158 | /* DRAM DVFS is disabled in recovery mode */ |
| 159 | if (CONFIG(MT8183_DRAM_DVFS) && !recovery_mode) |
| 160 | config |= DRAMC_CONFIG_DVFS; |
| 161 | |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 162 | /* Load calibration params from flash and run fast calibration */ |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 163 | if (recovery_mode) { |
| 164 | printk(BIOS_WARNING, "Skip loading cached calibration data\n"); |
Julius Werner | 0096167 | 2020-04-22 22:31:36 +0000 | [diff] [blame] | 165 | if (get_recovery_mode_retrain_switch()) { |
Yu-Ping Wu | 46009ea | 2019-10-17 13:38:32 +0800 | [diff] [blame] | 166 | printk(BIOS_WARNING, "Retrain memory in next boot\n"); |
| 167 | /* Use 0xFF as erased flash data. */ |
| 168 | memset(dparam, 0xff, sizeof(*dparam)); |
| 169 | dparam_ops->write_to_flash(dparam); |
| 170 | } |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 171 | } else if (dparam_ops->read_from_flash(dparam)) { |
| 172 | printk(BIOS_INFO, "DRAM-K: Fast Calibration\n"); |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 173 | if (dram_run_fast_calibration(dparam, config) == 0) { |
| 174 | printk(BIOS_INFO, |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 175 | "Calibration params loaded from flash\n"); |
Yu-Ping Wu | ffb5ea3 | 2019-10-07 15:55:57 +0800 | [diff] [blame] | 176 | if (mt_set_emi(dparam) == 0 && mt_mem_test() == 0) |
| 177 | return; |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 178 | } else { |
| 179 | printk(BIOS_ERR, |
| 180 | "Failed to apply cached calibration data\n"); |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 181 | } |
| 182 | } else { |
| 183 | printk(BIOS_WARNING, |
| 184 | "Failed to read calibration data from flash\n"); |
| 185 | } |
| 186 | |
Huayang Duan | 6e57b1c | 2020-07-23 13:53:39 +0800 | [diff] [blame] | 187 | const struct sdram_params *sdram_cfg = get_sdram_config(); |
| 188 | |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 189 | /* Run full calibration */ |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 190 | printk(BIOS_INFO, "DRAM-K: Full Calibration\n"); |
Huayang Duan | 6e57b1c | 2020-07-23 13:53:39 +0800 | [diff] [blame] | 191 | int err = dram_run_full_calibration(dparam, sdram_cfg->ddr_geometry, config); |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 192 | if (err == 0) { |
| 193 | printk(BIOS_INFO, "Successfully loaded DRAM blobs and " |
| 194 | "ran DRAM calibration\n"); |
Huayang Duan | e6ac20b | 2019-12-24 16:35:13 +0800 | [diff] [blame] | 195 | |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 196 | /* |
| 197 | * In recovery mode the system boots in RO but the flash params |
| 198 | * should be calibrated for RW so we can't mix them up. |
| 199 | */ |
| 200 | if (!recovery_mode) { |
| 201 | set_source_to_flash(dparam->freq_params); |
| 202 | dparam->header.checksum = compute_checksum(dparam); |
| 203 | dparam_ops->write_to_flash(dparam); |
| 204 | printk(BIOS_DEBUG, "Calibration params saved to flash: " |
| 205 | "version=%#x, size=%#x\n", |
| 206 | dparam->header.version, dparam->header.size); |
| 207 | } |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 208 | return; |
| 209 | } |
| 210 | |
| 211 | printk(BIOS_ERR, "Failed to do full calibration (%d), " |
| 212 | "falling back to load default sdram param\n", err); |
| 213 | |
| 214 | /* Init params from sdram configs and run partial calibration */ |
Yu-Ping Wu | 998a3cc | 2019-10-16 18:29:50 +0800 | [diff] [blame] | 215 | printk(BIOS_INFO, "DRAM-K: Partial Calibration\n"); |
Huayang Duan | 6e57b1c | 2020-07-23 13:53:39 +0800 | [diff] [blame] | 216 | init_sdram_params(dparam->freq_params, sdram_cfg); |
Yu-Ping Wu | ffb5ea3 | 2019-10-07 15:55:57 +0800 | [diff] [blame] | 217 | if (mt_set_emi(dparam) != 0) |
| 218 | die("Set emi failed with params from sdram config\n"); |
| 219 | if (mt_mem_test() != 0) |
| 220 | die("Memory test failed with params from sdram config\n"); |
Huayang Duan | 078332e | 2019-08-27 13:36:14 +0800 | [diff] [blame] | 221 | } |
Huayang Duan | e6ac20b | 2019-12-24 16:35:13 +0800 | [diff] [blame] | 222 | |
| 223 | void mt_mem_init(struct dramc_param_ops *dparam_ops) |
| 224 | { |
| 225 | mt_mem_init_run(dparam_ops); |
| 226 | |
| 227 | /* After DRAM calibration, restore vcore voltage to default setting */ |
| 228 | pmic_set_vcore_vol(800000); |
| 229 | } |