blob: b657708193df74b201fb248af1fdb2fec71511b5 [file] [log] [blame]
Huayang Duanc2ef1022018-09-26 14:24:02 +08001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2018 MediaTek Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
Huayang Duan4d15d2f2018-09-26 21:23:53 +080016#include <assert.h>
Huayang Duan078332e2019-08-27 13:36:14 +080017#include <cbfs.h>
Huayang Duan4d15d2f2018-09-26 21:23:53 +080018#include <console/console.h>
Yu-Ping Wue67dce02019-10-14 16:56:50 +080019#include <ip_checksum.h>
Huayang Duan078332e2019-08-27 13:36:14 +080020#include <soc/dramc_param.h>
Huayang Duan4d15d2f2018-09-26 21:23:53 +080021#include <soc/dramc_pi_api.h>
Huayang Duanc2ef1022018-09-26 14:24:02 +080022#include <soc/emi.h>
Huayang Duan4d15d2f2018-09-26 21:23:53 +080023#include <symbols.h>
Huayang Duanc2ef1022018-09-26 14:24:02 +080024
Yu-Ping Wuffb5ea32019-10-07 15:55:57 +080025static int mt_mem_test(void)
Huayang Duanc2ef1022018-09-26 14:24:02 +080026{
Huayang Duan4d15d2f2018-09-26 21:23:53 +080027 u64 rank_size[RANK_MAX];
28
Julius Wernercd49cce2019-03-05 16:53:33 -080029 if (CONFIG(MEMORY_TEST)) {
Huayang Duan4d15d2f2018-09-26 21:23:53 +080030 size_t r;
31 u8 *addr = _dram;
32
33 dramc_get_rank_size(rank_size);
34
35 for (r = RANK_0; r < RANK_MAX; r++) {
36 int i;
37
38 if (rank_size[r] == 0)
39 break;
40
41 i = complex_mem_test(addr, 0x2000);
42
43 printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s : %d\n",
44 (i == 0) ? "pass" : "fail", i);
45
Yu-Ping Wuffb5ea32019-10-07 15:55:57 +080046 if (i != 0) {
Yu-Ping Wu31ec0c42019-10-09 16:11:47 +080047 printk(BIOS_ERR, "DRAM memory test failed\n");
Yu-Ping Wuffb5ea32019-10-07 15:55:57 +080048 return -1;
49 }
Huayang Duan4d15d2f2018-09-26 21:23:53 +080050
51 addr += rank_size[r];
52 }
53 }
Yu-Ping Wuffb5ea32019-10-07 15:55:57 +080054
55 return 0;
Huayang Duanc2ef1022018-09-26 14:24:02 +080056}
Huayang Duan078332e2019-08-27 13:36:14 +080057
58static void dump_param_header(const struct dramc_param *dparam)
59{
60 const struct dramc_param_header *header = &dparam->header;
61
62 printk(BIOS_DEBUG, "header.status = %#x\n", header->status);
63 printk(BIOS_DEBUG, "header.magic = %#x (expected: %#x)\n",
64 header->magic, DRAMC_PARAM_HEADER_MAGIC);
65 printk(BIOS_DEBUG, "header.version = %#x (expected: %#x)\n",
66 header->version, DRAMC_PARAM_HEADER_VERSION);
67 printk(BIOS_DEBUG, "header.size = %#x (expected: %#lx)\n",
68 header->size, sizeof(*dparam));
69 printk(BIOS_DEBUG, "header.config = %#x\n", header->config);
70 printk(BIOS_DEBUG, "header.flags = %#x\n", header->flags);
71 printk(BIOS_DEBUG, "header.checksum = %#x\n", header->checksum);
72}
73
Yu-Ping Wue67dce02019-10-14 16:56:50 +080074static u32 compute_checksum(const struct dramc_param *dparam)
75{
76 return (u32)compute_ip_checksum(dparam->freq_params,
77 sizeof(dparam->freq_params));
78}
79
Huayang Duan078332e2019-08-27 13:36:14 +080080static int dram_run_fast_calibration(const struct dramc_param *dparam,
81 u16 config)
82{
83 if (!is_valid_dramc_param(dparam)) {
84 printk(BIOS_WARNING,
85 "Invalid DRAM calibration data from flash\n");
86 dump_param_header(dparam);
87 return -1;
88 }
89
Yu-Ping Wu31ec0c42019-10-09 16:11:47 +080090 if (dparam->header.config != config) {
Huayang Duan078332e2019-08-27 13:36:14 +080091 printk(BIOS_WARNING,
92 "Incompatible config for calibration data from flash "
93 "(expected: %#x, saved: %#x)\n",
94 config, dparam->header.config);
95 return -1;
96 }
97
Yu-Ping Wue67dce02019-10-14 16:56:50 +080098 const u32 checksum = compute_checksum(dparam);
99 if (dparam->header.checksum != checksum) {
100 printk(BIOS_ERR,
101 "Invalid DRAM calibration checksum from flash "
102 "(expected: %#x, saved: %#x)\n",
103 checksum, dparam->header.checksum);
104 return -1;
105 }
106
Huayang Duan078332e2019-08-27 13:36:14 +0800107 return 0;
108}
109
110static int dram_run_full_calibration(struct dramc_param *dparam, u16 config)
111{
112 initialize_dramc_param(dparam, config);
113
114 /* Load and run the provided blob for full-calibration if available */
115 struct prog dram = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/dram");
116
117 if (prog_locate(&dram))
118 return -1;
119
120 if (cbfs_prog_stage_load(&dram))
121 return -2;
122
Hung-Te Linbeeab4e2019-10-15 17:49:24 +0800123 dparam->do_putc = do_putchar;
Huayang Duan078332e2019-08-27 13:36:14 +0800124 prog_set_entry(&dram, prog_entry(&dram), dparam);
125 prog_run(&dram);
126
127 if (dparam->header.status != DRAMC_SUCCESS) {
128 printk(BIOS_ERR, "Full calibration failed: status = %d\n",
129 dparam->header.status);
130 return -3;
131 }
132
133 if (!(dparam->header.flags & DRAMC_FLAG_HAS_SAVED_DATA)) {
134 printk(BIOS_ERR,
135 "Full calibration executed without saving parameters. "
136 "Please ensure the blob is built properly.\n");
137 return -4;
138 }
139
140 return 0;
141}
142
143static void set_source_to_flash(struct sdram_params *freq_params)
144{
145 for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX;
146 shuffle++)
147 freq_params[shuffle].source = DRAMC_PARAM_SOURCE_FLASH;
148}
149
150static void init_sdram_params(struct sdram_params *dst,
151 const struct sdram_params *src)
152{
153 for (u8 shuffle = DRAM_DFS_SHUFFLE_1; shuffle < DRAM_DFS_SHUFFLE_MAX;
154 shuffle++)
155 memcpy(&dst[shuffle], src, sizeof(*dst));
156}
157
158void mt_mem_init(struct dramc_param_ops *dparam_ops)
159{
160 struct dramc_param *dparam = dparam_ops->param;
Huayang Duan078332e2019-08-27 13:36:14 +0800161
162 u16 config = 0;
163 if (CONFIG(MT8183_DRAM_EMCP))
164 config |= DRAMC_CONFIG_EMCP;
165
166 /* Load calibration params from flash and run fast calibration */
167 if (dparam_ops->read_from_flash(dparam)) {
168 if (dram_run_fast_calibration(dparam, config) == 0) {
169 printk(BIOS_INFO,
170 "DRAM calibraion params loaded from flash\n");
Yu-Ping Wuffb5ea32019-10-07 15:55:57 +0800171 if (mt_set_emi(dparam) == 0 && mt_mem_test() == 0)
172 return;
Huayang Duan078332e2019-08-27 13:36:14 +0800173 }
174 } else {
175 printk(BIOS_WARNING,
176 "Failed to read calibration data from flash\n");
177 }
178
179 /* Run full calibration */
180 int err = dram_run_full_calibration(dparam, config);
181 if (err == 0) {
182 printk(BIOS_INFO, "Successfully loaded DRAM blobs and "
183 "ran DRAM calibration\n");
184 set_source_to_flash(dparam->freq_params);
Yu-Ping Wue67dce02019-10-14 16:56:50 +0800185 dparam->header.checksum = compute_checksum(dparam);
Huayang Duan078332e2019-08-27 13:36:14 +0800186 dparam_ops->write_to_flash(dparam);
187 printk(BIOS_DEBUG, "Calibration params saved to flash: "
Yu-Ping Wu31ec0c42019-10-09 16:11:47 +0800188 "version=%#x, size=%#x\n",
Huayang Duan078332e2019-08-27 13:36:14 +0800189 dparam->header.version, dparam->header.size);
190 return;
191 }
192
193 printk(BIOS_ERR, "Failed to do full calibration (%d), "
194 "falling back to load default sdram param\n", err);
195
196 /* Init params from sdram configs and run partial calibration */
Yu-Ping Wu0e5b1962019-10-07 16:57:24 +0800197 init_sdram_params(dparam->freq_params, get_sdram_config());
Yu-Ping Wuffb5ea32019-10-07 15:55:57 +0800198 if (mt_set_emi(dparam) != 0)
199 die("Set emi failed with params from sdram config\n");
200 if (mt_mem_test() != 0)
201 die("Memory test failed with params from sdram config\n");
Huayang Duan078332e2019-08-27 13:36:14 +0800202}