Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Felix Held | dd882f3 | 2021-05-12 01:23:50 +0200 | [diff] [blame] | 3 | #include <acpi/acpigen.h> |
Raul E Rangel | 0b123dd | 2021-02-12 15:13:57 -0700 | [diff] [blame] | 4 | #include <amdblocks/acpi.h> |
Felix Held | dd882f3 | 2021-05-12 01:23:50 +0200 | [diff] [blame] | 5 | #include <amdblocks/alib.h> |
Arthur Heymans | ce17972 | 2023-06-07 15:27:18 +0200 | [diff] [blame] | 6 | #include <amdblocks/data_fabric.h> |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 7 | #include <amdblocks/ioapic.h> |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 8 | #include <amdblocks/iomap.h> |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 9 | #include <amdblocks/memmap.h> |
Felix Held | 3b3d802 | 2023-07-18 20:37:04 +0200 | [diff] [blame] | 10 | #include <amdblocks/root_complex.h> |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 11 | #include <arch/ioapic.h> |
Felix Held | a4ced63 | 2023-06-05 21:22:15 +0200 | [diff] [blame] | 12 | #include <arch/vga.h> |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 13 | #include <cbmem.h> |
| 14 | #include <console/console.h> |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 15 | #include <device/device.h> |
| 16 | #include <device/pci.h> |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 17 | #include <soc/iomap.h> |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 18 | #include <stdint.h> |
Felix Held | dd882f3 | 2021-05-12 01:23:50 +0200 | [diff] [blame] | 19 | #include "chip.h" |
| 20 | |
| 21 | #define DPTC_TOTAL_UPDATE_PARAMS 4 |
| 22 | |
| 23 | struct dptc_input { |
| 24 | uint16_t size; |
| 25 | struct alib_dptc_param params[DPTC_TOTAL_UPDATE_PARAMS]; |
| 26 | } __packed; |
| 27 | |
| 28 | #define DPTC_INPUTS(_thermctllmit, _sustained, _fast, _slow) \ |
| 29 | { \ |
| 30 | .size = sizeof(struct dptc_input), \ |
| 31 | .params = { \ |
| 32 | { \ |
| 33 | .id = ALIB_DPTC_THERMAL_CONTROL_LIMIT_ID, \ |
| 34 | .value = _thermctllmit, \ |
| 35 | }, \ |
| 36 | { \ |
| 37 | .id = ALIB_DPTC_SUSTAINED_POWER_LIMIT_ID, \ |
| 38 | .value = _sustained, \ |
| 39 | }, \ |
| 40 | { \ |
| 41 | .id = ALIB_DPTC_FAST_PPT_LIMIT_ID, \ |
| 42 | .value = _fast, \ |
| 43 | }, \ |
| 44 | { \ |
| 45 | .id = ALIB_DPTC_SLOW_PPT_LIMIT_ID, \ |
| 46 | .value = _slow, \ |
| 47 | }, \ |
| 48 | }, \ |
| 49 | } |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 50 | |
| 51 | /* |
| 52 | * |
| 53 | * +--------------------------------+ |
| 54 | * | | |
| 55 | * | | |
| 56 | * | | |
| 57 | * | | |
| 58 | * | | |
| 59 | * | | |
| 60 | * | | |
| 61 | * reserved_dram_end +--------------------------------+ |
| 62 | * | | |
| 63 | * | verstage (if reqd) | |
| 64 | * | (VERSTAGE_SIZE) | |
| 65 | * +--------------------------------+ VERSTAGE_ADDR |
| 66 | * | | |
| 67 | * | FSP-M | |
| 68 | * | (FSP_M_SIZE) | |
| 69 | * +--------------------------------+ FSP_M_ADDR |
| 70 | * | romstage | |
| 71 | * | (ROMSTAGE_SIZE) | |
| 72 | * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END |
| 73 | * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 |
| 74 | * | bootblock | |
| 75 | * | (C_ENV_BOOTBLOCK_SIZE) | |
| 76 | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE |
| 77 | * | Unused hole | |
| 78 | * | (86KiB) | |
| 79 | * +--------------------------------+ |
| 80 | * | FMAP cache (FMAP_SIZE) | |
| 81 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 |
| 82 | * | Early Timestamp region (512B) | |
| 83 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE |
| 84 | * | Preram CBMEM console | |
| 85 | * | (PRERAM_CBMEM_CONSOLE_SIZE) | |
| 86 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE |
| 87 | * | PSP shared (vboot workbuf) | |
| 88 | * | (PSP_SHAREDMEM_SIZE) | |
| 89 | * +--------------------------------+ PSP_SHAREDMEM_BASE |
| 90 | * | APOB (64KiB) | |
| 91 | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS |
| 92 | * | Early BSP stack | |
| 93 | * | (EARLYRAM_BSP_STACK_SIZE) | |
| 94 | * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE |
| 95 | * | DRAM | |
| 96 | * +--------------------------------+ 0x100000 |
| 97 | * | Option ROM | |
| 98 | * +--------------------------------+ 0xc0000 |
| 99 | * | Legacy VGA | |
| 100 | * +--------------------------------+ 0xa0000 |
| 101 | * | DRAM | |
| 102 | * +--------------------------------+ 0x0 |
| 103 | */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 104 | void read_soc_memmap_resources(struct device *dev, unsigned long *idx) |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 105 | { |
| 106 | uint32_t mem_usable = (uintptr_t)cbmem_top(); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 107 | |
| 108 | uintptr_t early_reserved_dram_start, early_reserved_dram_end; |
| 109 | const struct memmap_early_dram *e = memmap_get_early_dram_usage(); |
| 110 | |
| 111 | early_reserved_dram_start = e->base; |
| 112 | early_reserved_dram_end = e->base + e->size; |
| 113 | |
| 114 | /* 0x0 - 0x9ffff */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 115 | ram_range(dev, (*idx)++, 0, 0xa0000); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 116 | |
| 117 | /* 0xa0000 - 0xbffff: legacy VGA */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 118 | mmio_range(dev, (*idx)++, VGA_MMIO_BASE, VGA_MMIO_SIZE); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 119 | |
| 120 | /* 0xc0000 - 0xfffff: Option ROM */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 121 | reserved_ram_from_to(dev, (*idx)++, 0xc0000, 1 * MiB); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 122 | |
| 123 | /* 1MiB - bottom of DRAM reserved for early coreboot usage */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 124 | ram_from_to(dev, (*idx)++, 1 * MiB, early_reserved_dram_start); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 125 | |
| 126 | /* DRAM reserved for early coreboot usage */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 127 | reserved_ram_from_to(dev, (*idx)++, early_reserved_dram_start, early_reserved_dram_end); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 128 | |
| 129 | /* |
| 130 | * top of DRAM consumed early - low top usable RAM |
| 131 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
| 132 | */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 133 | ram_from_to(dev, (*idx)++, early_reserved_dram_end, mem_usable); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 134 | |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 135 | /* Reserve fixed IOMMU MMIO region */ |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 136 | mmio_range(dev, (*idx)++, IOMMU_RESERVED_MMIO_BASE, IOMMU_RESERVED_MMIO_SIZE); |
Felix Held | 12a4482 | 2023-06-02 15:30:50 +0200 | [diff] [blame] | 137 | |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 138 | read_fsp_resources(dev, idx); |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 139 | } |
| 140 | |
| 141 | static void root_complex_init(struct device *dev) |
| 142 | { |
Kyösti Mälkki | 2e65e9c | 2021-06-16 11:00:40 +0300 | [diff] [blame] | 143 | register_new_ioapic((u8 *)GNB_IO_APIC_ADDR); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Felix Held | dd882f3 | 2021-05-12 01:23:50 +0200 | [diff] [blame] | 146 | static void acipgen_dptci(void) |
| 147 | { |
| 148 | const struct soc_amd_cezanne_config *config = config_of_soc(); |
| 149 | |
Tim Van Patten | 9eac097 | 2022-09-13 15:34:08 -0600 | [diff] [blame] | 150 | /* Normal mode DPTC values. */ |
Felix Held | dd882f3 | 2021-05-12 01:23:50 +0200 | [diff] [blame] | 151 | struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, |
Tim Van Patten | 9244358 | 2022-08-23 16:06:33 -0600 | [diff] [blame] | 152 | config->sustained_power_limit_mW, |
| 153 | config->fast_ppt_limit_mW, |
| 154 | config->slow_ppt_limit_mW); |
| 155 | acpigen_write_alib_dptc_default((uint8_t *)&default_input, sizeof(default_input)); |
Felix Held | dd882f3 | 2021-05-12 01:23:50 +0200 | [diff] [blame] | 156 | } |
| 157 | |
Raul E Rangel | 0b123dd | 2021-02-12 15:13:57 -0700 | [diff] [blame] | 158 | static void root_complex_fill_ssdt(const struct device *device) |
| 159 | { |
Tim Van Patten | 9eac097 | 2022-09-13 15:34:08 -0600 | [diff] [blame] | 160 | if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) |
| 161 | acipgen_dptci(); |
Raul E Rangel | 0b123dd | 2021-02-12 15:13:57 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Felix Held | b2840130 | 2021-02-17 00:05:34 +0100 | [diff] [blame] | 164 | static const char *gnb_acpi_name(const struct device *dev) |
| 165 | { |
| 166 | return "GNB"; |
| 167 | } |
| 168 | |
Arthur Heymans | b65f609 | 2022-10-05 21:45:23 +0200 | [diff] [blame] | 169 | struct device_operations cezanne_root_complex_operations = { |
Felix Held | 30f36c3 | 2024-01-30 15:15:31 +0100 | [diff] [blame] | 170 | /* The root complex has no PCI BARs implemented, so there's no need to call |
| 171 | pci_dev_read_resources for it */ |
| 172 | .read_resources = noop_read_resources, |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 173 | .set_resources = noop_set_resources, |
| 174 | .enable_resources = pci_dev_enable_resources, |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame] | 175 | .init = root_complex_init, |
Felix Held | b2840130 | 2021-02-17 00:05:34 +0100 | [diff] [blame] | 176 | .acpi_name = gnb_acpi_name, |
Raul E Rangel | 0b123dd | 2021-02-12 15:13:57 -0700 | [diff] [blame] | 177 | .acpi_fill_ssdt = root_complex_fill_ssdt, |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 178 | }; |
Felix Held | 3b3d802 | 2023-07-18 20:37:04 +0200 | [diff] [blame] | 179 | |
| 180 | uint32_t get_iohc_misc_smn_base(struct device *domain) |
| 181 | { |
Felix Held | 69ffebf | 2023-07-24 21:31:44 +0200 | [diff] [blame] | 182 | return SMN_IOHC_MISC_BASE_13B1; |
Felix Held | 3b3d802 | 2023-07-18 20:37:04 +0200 | [diff] [blame] | 183 | } |
| 184 | |
| 185 | static const struct non_pci_mmio_reg non_pci_mmio[] = { |
| 186 | { 0x2d8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 187 | { 0x2e0, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 188 | { 0x2e8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 189 | /* The hardware has a 256 byte alignment requirement for the IOAPIC MMIO base, but we |
| 190 | tell the FSP to configure a 4k-aligned base address and this is reported as 4 KiB |
| 191 | resource. */ |
| 192 | { 0x2f0, 0xffffffffff00ull, 4 * KiB, IOMMU_IOAPIC_IDX }, |
| 193 | { 0x2f8, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 194 | { 0x300, 0xfffffff00000ull, 1 * MiB, NON_PCI_RES_IDX_AUTO }, |
| 195 | { 0x308, 0xfffffffff000ull, 4 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 196 | { 0x318, 0xfffffff80000ull, 512 * KiB, NON_PCI_RES_IDX_AUTO }, |
| 197 | }; |
| 198 | |
| 199 | const struct non_pci_mmio_reg *get_iohc_non_pci_mmio_regs(size_t *count) |
| 200 | { |
| 201 | *count = ARRAY_SIZE(non_pci_mmio); |
| 202 | return non_pci_mmio; |
| 203 | } |
Felix Held | b0ab545 | 2023-08-11 22:24:00 +0200 | [diff] [blame] | 204 | |
| 205 | signed int get_iohc_fabric_id(struct device *domain) |
| 206 | { |
| 207 | switch (domain->path.domain.domain) { |
| 208 | case 0: |
| 209 | return IOMS0_FABRIC_ID; |
| 210 | default: |
| 211 | return -1; |
| 212 | } |
| 213 | } |