Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Raul E Rangel | 0b123dd | 2021-02-12 15:13:57 -0700 | [diff] [blame] | 3 | #include <amdblocks/acpi.h> |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame^] | 4 | #include <amdblocks/ioapic.h> |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 5 | #include <amdblocks/memmap.h> |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame^] | 6 | #include <arch/ioapic.h> |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 7 | #include <cbmem.h> |
| 8 | #include <console/console.h> |
| 9 | #include <cpu/amd/msr.h> |
| 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
| 12 | #include <device/pci_ids.h> |
| 13 | #include <fsp/util.h> |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame^] | 14 | #include <soc/iomap.h> |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 15 | #include <stdint.h> |
| 16 | |
| 17 | /* |
| 18 | * |
| 19 | * +--------------------------------+ |
| 20 | * | | |
| 21 | * | | |
| 22 | * | | |
| 23 | * | | |
| 24 | * | | |
| 25 | * | | |
| 26 | * | | |
| 27 | * reserved_dram_end +--------------------------------+ |
| 28 | * | | |
| 29 | * | verstage (if reqd) | |
| 30 | * | (VERSTAGE_SIZE) | |
| 31 | * +--------------------------------+ VERSTAGE_ADDR |
| 32 | * | | |
| 33 | * | FSP-M | |
| 34 | * | (FSP_M_SIZE) | |
| 35 | * +--------------------------------+ FSP_M_ADDR |
| 36 | * | romstage | |
| 37 | * | (ROMSTAGE_SIZE) | |
| 38 | * +--------------------------------+ ROMSTAGE_ADDR = BOOTBLOCK_END |
| 39 | * | | X86_RESET_VECTOR = BOOTBLOCK_END - 0x10 |
| 40 | * | bootblock | |
| 41 | * | (C_ENV_BOOTBLOCK_SIZE) | |
| 42 | * +--------------------------------+ BOOTBLOCK_ADDR = BOOTBLOCK_END - C_ENV_BOOTBLOCK_SIZE |
| 43 | * | Unused hole | |
| 44 | * | (86KiB) | |
| 45 | * +--------------------------------+ |
| 46 | * | FMAP cache (FMAP_SIZE) | |
| 47 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200 |
| 48 | * | Early Timestamp region (512B) | |
| 49 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE + PRERAM_CBMEM_CONSOLE_SIZE |
| 50 | * | Preram CBMEM console | |
| 51 | * | (PRERAM_CBMEM_CONSOLE_SIZE) | |
| 52 | * +--------------------------------+ PSP_SHAREDMEM_BASE + PSP_SHAREDMEM_SIZE |
| 53 | * | PSP shared (vboot workbuf) | |
| 54 | * | (PSP_SHAREDMEM_SIZE) | |
| 55 | * +--------------------------------+ PSP_SHAREDMEM_BASE |
| 56 | * | APOB (64KiB) | |
| 57 | * +--------------------------------+ PSP_APOB_DRAM_ADDRESS |
| 58 | * | Early BSP stack | |
| 59 | * | (EARLYRAM_BSP_STACK_SIZE) | |
| 60 | * reserved_dram_start +--------------------------------+ EARLY_RESERVED_DRAM_BASE |
| 61 | * | DRAM | |
| 62 | * +--------------------------------+ 0x100000 |
| 63 | * | Option ROM | |
| 64 | * +--------------------------------+ 0xc0000 |
| 65 | * | Legacy VGA | |
| 66 | * +--------------------------------+ 0xa0000 |
| 67 | * | DRAM | |
| 68 | * +--------------------------------+ 0x0 |
| 69 | */ |
| 70 | static void read_resources(struct device *dev) |
| 71 | { |
| 72 | uint32_t mem_usable = (uintptr_t)cbmem_top(); |
| 73 | unsigned int idx = 0; |
| 74 | const struct hob_header *hob = fsp_get_hob_list(); |
| 75 | const struct hob_resource *res; |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame^] | 76 | struct resource *gnb_apic; |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 77 | |
| 78 | uintptr_t early_reserved_dram_start, early_reserved_dram_end; |
| 79 | const struct memmap_early_dram *e = memmap_get_early_dram_usage(); |
| 80 | |
| 81 | early_reserved_dram_start = e->base; |
| 82 | early_reserved_dram_end = e->base + e->size; |
| 83 | |
| 84 | /* 0x0 - 0x9ffff */ |
| 85 | ram_resource(dev, idx++, 0, 0xa0000 / KiB); |
| 86 | |
| 87 | /* 0xa0000 - 0xbffff: legacy VGA */ |
| 88 | mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); |
| 89 | |
| 90 | /* 0xc0000 - 0xfffff: Option ROM */ |
| 91 | reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); |
| 92 | |
| 93 | /* 1MiB - bottom of DRAM reserved for early coreboot usage */ |
| 94 | ram_resource(dev, idx++, (1 * MiB) / KiB, |
| 95 | (early_reserved_dram_start - (1 * MiB)) / KiB); |
| 96 | |
| 97 | /* DRAM reserved for early coreboot usage */ |
| 98 | reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB, |
| 99 | (early_reserved_dram_end - early_reserved_dram_start) / KiB); |
| 100 | |
| 101 | /* |
| 102 | * top of DRAM consumed early - low top usable RAM |
| 103 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
| 104 | */ |
| 105 | ram_resource(dev, idx++, early_reserved_dram_end / KiB, |
| 106 | (mem_usable - early_reserved_dram_end) / KiB); |
| 107 | |
| 108 | mmconf_resource(dev, MMIO_CONF_BASE); |
| 109 | |
| 110 | if (!hob) { |
| 111 | printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", |
| 112 | __func__); |
| 113 | return; |
| 114 | } |
| 115 | |
| 116 | for (; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = fsp_next_hob(hob)) { |
| 117 | |
| 118 | if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) |
| 119 | continue; |
| 120 | |
| 121 | res = fsp_hob_header_to_resource(hob); |
| 122 | |
| 123 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY && res->addr < mem_usable) |
| 124 | continue; /* 0 through low usable was set above */ |
| 125 | if (res->type == EFI_RESOURCE_MEMORY_MAPPED_IO) |
| 126 | continue; /* Done separately */ |
| 127 | |
| 128 | if (res->type == EFI_RESOURCE_SYSTEM_MEMORY) |
| 129 | ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); |
| 130 | else if (res->type == EFI_RESOURCE_MEMORY_RESERVED) |
| 131 | reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB); |
| 132 | else |
| 133 | printk(BIOS_ERR, "Error: failed to set resources for type %d\n", |
| 134 | res->type); |
| 135 | } |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame^] | 136 | |
| 137 | /* GNB IOAPIC resource */ |
| 138 | gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); |
| 139 | gnb_apic->base = GNB_IO_APIC_ADDR; |
| 140 | gnb_apic->size = 0x00001000; |
| 141 | gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 142 | } |
| 143 | |
| 144 | static void root_complex_init(struct device *dev) |
| 145 | { |
| 146 | setup_ioapic((u8 *)GNB_IO_APIC_ADDR, GNB_IOAPIC_ID); |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 147 | } |
| 148 | |
Raul E Rangel | 0b123dd | 2021-02-12 15:13:57 -0700 | [diff] [blame] | 149 | static void root_complex_fill_ssdt(const struct device *device) |
| 150 | { |
| 151 | acpi_fill_root_complex_tom(device); |
| 152 | } |
| 153 | |
Felix Held | b2840130 | 2021-02-17 00:05:34 +0100 | [diff] [blame] | 154 | static const char *gnb_acpi_name(const struct device *dev) |
| 155 | { |
| 156 | return "GNB"; |
| 157 | } |
| 158 | |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 159 | static struct device_operations root_complex_operations = { |
| 160 | .read_resources = read_resources, |
| 161 | .set_resources = noop_set_resources, |
| 162 | .enable_resources = pci_dev_enable_resources, |
Felix Held | 1ed5a63 | 2021-05-04 21:51:43 +0200 | [diff] [blame^] | 163 | .init = root_complex_init, |
Felix Held | b2840130 | 2021-02-17 00:05:34 +0100 | [diff] [blame] | 164 | .acpi_name = gnb_acpi_name, |
Raul E Rangel | 0b123dd | 2021-02-12 15:13:57 -0700 | [diff] [blame] | 165 | .acpi_fill_ssdt = root_complex_fill_ssdt, |
Raul E Rangel | cf6dc7d | 2021-02-05 16:00:41 -0700 | [diff] [blame] | 166 | }; |
| 167 | |
| 168 | static const struct pci_driver family17_root_complex __pci_driver = { |
| 169 | .ops = &root_complex_operations, |
| 170 | .vendor = PCI_VENDOR_ID_AMD, |
| 171 | .device = PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB, |
| 172 | }; |