Gitiles
Code Review Sign In
review.coreboot.org / coreboot / ddcb7f1cc410577726f1c34842cf3065ac985ec0 / . / src / drivers / usb / pci_ehci.c
blob: 8e854264a2085de65ba7985ec7ee7786f56b692e [file] [log] [blame]
Angel Pons8a3453f2020-04-02 23:48:19 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]2
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]3#include <console/console.h>
4#include <device/pci_ehci.h>
Kyösti Mälkki13f66502019-03-03 08:01:05 +0200[diff] [blame]5#include <device/mmio.h>
Kyösti Mälkkif1b58b72019-03-01 13:43:02 +0200[diff] [blame]6#include <device/pci_ops.h>
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]7#include <device/pci.h>
8#include <device/pci_def.h>
9#include <string.h>
10
11#include "ehci_debug.h"
12#include "ehci.h"
13
Kyösti Mälkkid07f3772017-09-07 19:16:27 +0300[diff] [blame]14#if ENV_RAMSTAGE
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]15static struct device_operations *ehci_drv_ops;
16static struct device_operations ehci_dbg_ops;
17#endif
18
Kyösti Mälkki6f6a2492014-02-09 19:21:30 +0200[diff] [blame]19int ehci_debug_hw_enable(unsigned int *base, unsigned int *dbg_offset)
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]20{
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]21 pci_devfn_t dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
Kyösti Mälkki6683e402017-07-30 13:23:32 +0300[diff] [blame]22
Kyösti Mälkki5bd92642019-01-06 16:13:07 +0200[diff] [blame]23 /* We only support controllers on bus 0. */
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]24 if (PCI_DEV2SEGBUS(dev) != 0)
Kyösti Mälkki5bd92642019-01-06 16:13:07 +0200[diff] [blame]25 return -1;
26
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]27 u32 class = pci_s_read_config32(dev, PCI_CLASS_REVISION) >> 8;
Kyösti Mälkki6683e402017-07-30 13:23:32 +0300[diff] [blame]28 if (class != PCI_EHCI_CLASSCODE)
29 return -1;
30
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]31 u8 pm_cap = pci_s_find_capability(dev, PCI_CAP_ID_PM);
Kyösti Mälkki6aea6f72017-07-30 09:01:24 +0300[diff] [blame]32 if (pm_cap) {
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]33 u16 pm_ctrl = pci_s_read_config16(dev, pm_cap + PCI_PM_CTRL);
Kyösti Mälkki6aea6f72017-07-30 09:01:24 +0300[diff] [blame]34 /* Set to D0 and disable PM events. */
35 pm_ctrl &= ~PCI_PM_CTRL_PME_ENABLE;
36 pm_ctrl &= ~PCI_PM_CTRL_STATE_MASK;
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]37 pci_s_write_config16(dev, pm_cap + PCI_PM_CTRL, pm_ctrl);
Kyösti Mälkki6aea6f72017-07-30 09:01:24 +0300[diff] [blame]38 }
39
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]40 u8 pos = pci_s_find_capability(dev, PCI_CAP_ID_EHCI_DEBUG);
Kyösti Mälkki6f6a2492014-02-09 19:21:30 +0200[diff] [blame]41 if (!pos)
42 return -1;
43
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]44 u32 cap = pci_s_read_config32(dev, pos);
Kyösti Mälkki6f6a2492014-02-09 19:21:30 +0200[diff] [blame]45
46 /* FIXME: We should remove static EHCI_BAR_INDEX. */
Kyösti Mälkkid1a0c572017-07-30 11:37:14 +0300[diff] [blame]47 u8 ehci_bar = 0x10 + 4 * ((cap >> 29) - 1);
48 if (ehci_bar != EHCI_BAR_INDEX)
Kyösti Mälkki6f6a2492014-02-09 19:21:30 +0200[diff] [blame]49 return -1;
50
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]51 pci_s_write_config32(dev, ehci_bar, CONFIG_EHCI_BAR);
Kyösti Mälkkid1a0c572017-07-30 11:37:14 +0300[diff] [blame]52
Kyösti Mälkkif2cc3dd2019-09-27 18:09:52 +0300[diff] [blame]53 pci_s_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY |
Kyösti Mälkkid1a0c572017-07-30 11:37:14 +0300[diff] [blame]54 PCI_COMMAND_MASTER);
55
Kyösti Mälkki6f6a2492014-02-09 19:21:30 +0200[diff] [blame]56 *base = CONFIG_EHCI_BAR;
57 *dbg_offset = (cap>>16) & 0x1ffc;
Kyösti Mälkkid1a0c572017-07-30 11:37:14 +0300[diff] [blame]58
Kyösti Mälkki6f6a2492014-02-09 19:21:30 +0200[diff] [blame]59 return 0;
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]60}
61
62void ehci_debug_select_port(unsigned int port)
63{
64 pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
65 pci_ehci_dbg_set_port(dbg_dev, port);
66}
67
Kyösti Mälkkid07f3772017-09-07 19:16:27 +0300[diff] [blame]68#if ENV_RAMSTAGE
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]69static void pci_ehci_set_resources(struct device *dev)
70{
71 struct resource *res;
72
73 printk(BIOS_DEBUG, "%s EHCI Debug Port hook triggered\n", dev_path(dev));
74 usbdebug_disable();
75
76 if (ehci_drv_ops->set_resources)
77 ehci_drv_ops->set_resources(dev);
Angel Ponse0588412021-11-03 13:22:22 +0100[diff] [blame]78 res = probe_resource(dev, EHCI_BAR_INDEX);
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]79 if (!res)
80 return;
81
82 usbdebug_re_enable((u32)res->base);
83 report_resource_stored(dev, res, "");
84 printk(BIOS_DEBUG, "%s EHCI Debug Port relocated\n", dev_path(dev));
85}
86
87void pci_ehci_read_resources(struct device *dev)
88{
89 pci_devfn_t dbg_dev = pci_ehci_dbg_dev(CONFIG_USBDEBUG_HCD_INDEX);
90
91 if (!ehci_drv_ops && pci_match_simple_dev(dev, dbg_dev)) {
92 memcpy(&ehci_dbg_ops, dev->ops, sizeof(ehci_dbg_ops));
93 ehci_drv_ops = dev->ops;
94 ehci_dbg_ops.set_resources = pci_ehci_set_resources;
95 dev->ops = &ehci_dbg_ops;
96 printk(BIOS_DEBUG, "%s EHCI BAR hook registered\n", dev_path(dev));
97 } else {
98 printk(BIOS_DEBUG, "More than one caller of %s from %s\n", __func__, dev_path(dev));
99 }
100
101 pci_dev_read_resources(dev);
102}
103#endif
104
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800[diff] [blame]105u8 *pci_ehci_base_regs(pci_devfn_t sdev)
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]106{
Patrick Rudolphae64f222019-11-30 09:42:20 +0100[diff] [blame]107 u32 bar = pci_s_read_config32(sdev, EHCI_BAR_INDEX) & ~0x0f;
108 u8 *base = (u8 *)(uintptr_t)bar;
Kyösti Mälkkicb141bc2014-02-07 19:24:23 +0200[diff] [blame]109 return base + HC_LENGTH(read32(base));
110}