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Jonathan Zhang3ed903f2023-01-25 11:37:27 -08001## SPDX-License-Identifier: GPL-2.0-only
2
3ifeq ($(CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP),y)
4
5subdirs-y += ../../../../cpu/intel/turbo
6subdirs-y += ../../../../cpu/x86/lapic
7subdirs-y += ../../../../cpu/x86/mtrr
8subdirs-y += ../../../../cpu/x86/tsc
9subdirs-y += ../../../../cpu/intel/microcode
10
Jincheng Li31998022024-03-13 15:06:26 +080011romstage-y += romstage.c soc_util.c
Jonathan Zhang3ed903f2023-01-25 11:37:27 -080012romstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
13romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
14
Patrick Rudolphcb92d282024-03-21 08:05:03 +010015ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c reset.c
Arthur Heymans550f55e2022-08-24 14:44:26 +020016ramstage-y += crashlog.c ioat.c
Shuo Liuec58beb2024-03-11 07:14:07 +080017ramstage-y += ../chip_gen1.c
Jonathan Zhang3ed903f2023-01-25 11:37:27 -080018ramstage-$(CONFIG_DISPLAY_HOBS) += hob_display.c
19ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c
Jonathan Zhang3ed903f2023-01-25 11:37:27 -080020CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/spr/include -I$(src)/soc/intel/xeon_sp/spr
21
Patrick Rudolphdc735c12024-04-04 08:49:19 +020022cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8f-08
23cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-cf-02
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Jonathan Zhang3ed903f2023-01-25 11:37:27 -080025endif ## CONFIG_SOC_INTEL_SAPPHIRERAPIDS_SP