Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Martin Roth | f643a4d | 2023-09-27 16:46:46 -0600 | [diff] [blame] | 3 | #include <FCH/Common/FchCommonCfg.h> |
Arthur Heymans | 62389ab | 2023-07-14 20:11:15 +0200 | [diff] [blame] | 4 | #include <FCH/Common/FchCore/FchSata/FchSata.h> |
Arthur Heymans | 81ceea1 | 2023-07-14 19:56:03 +0200 | [diff] [blame] | 5 | #include <RcMgr/DfX/RcManager4-api.h> |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 6 | #include <amdblocks/reset.h> |
| 7 | #include <bootstate.h> |
| 8 | #include <cbmem.h> |
Arthur Heymans | 81ceea1 | 2023-07-14 19:56:03 +0200 | [diff] [blame] | 9 | #include <cpu/cpu.h> |
Martin Roth | f643a4d | 2023-09-27 16:46:46 -0600 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <soc/soc_chip.h> |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 12 | #include <xSIM-api.h> |
| 13 | #include "opensil_console.h" |
Arthur Heymans | 5f6cf61 | 2023-07-14 22:37:03 +0200 | [diff] [blame] | 14 | #include "opensil.h" |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 15 | |
Arthur Heymans | 5f6cf61 | 2023-07-14 22:37:03 +0200 | [diff] [blame] | 16 | void SIL_STATUS_report(const char *function, const int status) |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 17 | { |
| 18 | const int log_level = status == SilPass ? BIOS_DEBUG : BIOS_ERR; |
| 19 | const char *error_string = "Unkown error"; |
| 20 | |
| 21 | const struct error_string_entry { |
| 22 | SIL_STATUS status; |
| 23 | const char *string; |
| 24 | } errors[] = { |
| 25 | {SilPass, "SilPass"}, |
| 26 | {SilUnsupportedHardware, "SilUnsupportedHardware"}, |
| 27 | {SilUnsupported, "SilUnsupported"}, |
| 28 | {SilInvalidParameter, "SilInvalidParameter"}, |
| 29 | {SilAborted, "SilAborted"}, |
| 30 | {SilOutOfResources, "SilOutOfResources"}, |
| 31 | {SilNotFound, "SilNotFound"}, |
| 32 | {SilOutOfBounds, "SilOutOfBounds"}, |
| 33 | {SilDeviceError, "SilDeviceError"}, |
| 34 | {SilResetRequestColdImm, "SilResetRequestColdImm"}, |
| 35 | {SilResetRequestColdDef, "SilResetRequestColdDef"}, |
| 36 | {SilResetRequestWarmImm, "SilResetRequestWarmImm"}, |
| 37 | {SilResetRequestWarmDef, "SilResetRequestWarmDef"}, |
| 38 | }; |
| 39 | |
| 40 | int i; |
| 41 | for (i = 0; i < ARRAY_SIZE(errors); i++) { |
| 42 | if (errors[i].status == status) |
| 43 | error_string = errors[i].string; |
| 44 | } |
| 45 | printk(log_level, "%s returned %d (%s)\n", function, status, error_string); |
| 46 | } |
| 47 | |
Arthur Heymans | 81ceea1 | 2023-07-14 19:56:03 +0200 | [diff] [blame] | 48 | static void setup_rc_manager_default(void) |
| 49 | { |
| 50 | DFX_RCMGR_INPUT_BLK *rc_mgr_input_block = SilFindStructure(SilId_RcManager, 0); |
| 51 | /* Let openSIL distribute the resources to the different PCI roots */ |
| 52 | rc_mgr_input_block->SetRcBasedOnNv = false; |
| 53 | |
| 54 | /* Currently 1P is the only supported configuration */ |
| 55 | rc_mgr_input_block->SocketNumber = 1; |
| 56 | rc_mgr_input_block->RbsPerSocket = 4; /* PCI root bridges per socket */ |
| 57 | rc_mgr_input_block->McptEnable = true; |
| 58 | rc_mgr_input_block->PciExpressBaseAddress = CONFIG_ECAM_MMCONF_BASE_ADDRESS; |
| 59 | rc_mgr_input_block->BottomMmioReservedForPrimaryRb = 4ull * GiB - 32 * MiB; |
| 60 | rc_mgr_input_block->MmioSizePerRbForNonPciDevice = 16 * MiB; |
| 61 | /* MmioAbove4GLimit will be adjusted down in openSIL */ |
| 62 | rc_mgr_input_block->MmioAbove4GLimit = POWER_OF_2(cpu_phys_address_size()); |
| 63 | rc_mgr_input_block->Above4GMmioSizePerRbForNonPciDevice = 0; |
| 64 | } |
| 65 | |
Martin Roth | f643a4d | 2023-09-27 16:46:46 -0600 | [diff] [blame] | 66 | #define NUM_XHCI_CONTROLLERS 2 |
| 67 | static void configure_usb(void) |
| 68 | { |
Felix Held | d123f8d | 2023-12-15 10:57:30 +0100 | [diff] [blame] | 69 | const struct soc_amd_genoa_poc_config *soc_config = config_of_soc(); |
Martin Roth | f643a4d | 2023-09-27 16:46:46 -0600 | [diff] [blame] | 70 | const struct soc_usb_config *usb = &soc_config->usb; |
| 71 | |
| 72 | FCHUSB_INPUT_BLK *fch_usb_data = SilFindStructure(SilId_FchUsb, 0); |
| 73 | fch_usb_data->Xhci0Enable = usb->xhci0_enable; |
| 74 | fch_usb_data->Xhci1Enable = usb->xhci1_enable; |
| 75 | fch_usb_data->Xhci2Enable = false; /* there's no XHCI2 on this SoC */ |
| 76 | for (int i = 0; i < NUM_XHCI_CONTROLLERS; i++) { |
| 77 | memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb20OcPin, &usb->usb2_oc_pins[i], |
| 78 | sizeof(fch_usb_data->XhciOCpinSelect[i].Usb20OcPin)); |
| 79 | memcpy(&fch_usb_data->XhciOCpinSelect[i].Usb31OcPin, &usb->usb3_oc_pins[i], |
| 80 | sizeof(fch_usb_data->XhciOCpinSelect[i].Usb31OcPin)); |
| 81 | } |
| 82 | fch_usb_data->XhciOcPolarityCfgLow = usb->polarity_cfg_low; |
| 83 | fch_usb_data->Usb3PortForceGen1 = usb->usb3_force_gen1.raw; |
| 84 | |
| 85 | /* Instead of overwriting the whole OemUsbConfigurationTable, only copy the relevant |
| 86 | fields to the pre-populated data structure */ |
| 87 | fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->usb31_phy_enable; |
| 88 | if (usb->usb31_phy_enable) |
| 89 | memcpy(&fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort, usb->usb31_phy, |
| 90 | sizeof(fch_usb_data->OemUsbConfigurationTable.Usb31PhyPort)); |
| 91 | fch_usb_data->OemUsbConfigurationTable.Usb31PhyEnable = usb->s1_usb31_phy_enable; |
| 92 | if (usb->s1_usb31_phy_enable) |
| 93 | memcpy(&fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort, usb->s1_usb31_phy, |
| 94 | sizeof(fch_usb_data->OemUsbConfigurationTable.S1Usb31PhyPort)); |
| 95 | } |
| 96 | |
Arthur Heymans | 62389ab | 2023-07-14 20:11:15 +0200 | [diff] [blame] | 97 | #define NUM_SATA_CONTROLLERS 4 |
| 98 | static void configure_sata(void) |
| 99 | { |
| 100 | FCHSATA_INPUT_BLK *fch_sata_data = SilFindStructure(SilId_FchSata, 0); |
| 101 | FCH_SATA2 *fch_sata_defaults = GetFchSataData(); |
| 102 | for (int i = 0; i < NUM_SATA_CONTROLLERS; i++) { |
| 103 | fch_sata_data[i] = fch_sata_defaults[i]; |
| 104 | fch_sata_data[i].SataSetMaxGen2 = false; |
| 105 | fch_sata_data[i].SataMsiEnable = true; |
| 106 | fch_sata_data[i].SataEspPort = 0xFF; |
| 107 | fch_sata_data[i].SataRasSupport = true; |
| 108 | fch_sata_data[i].SataDevSlpPort1Num = 1; |
| 109 | fch_sata_data[i].SataMsiEnable = true; |
| 110 | fch_sata_data[i].SataControllerAutoShutdown = true; |
| 111 | fch_sata_data[i].SataRxPolarity = 0xFF; |
| 112 | } |
| 113 | } |
| 114 | |
Felix Held | dc12a38 | 2024-01-16 00:50:46 +0100 | [diff] [blame^] | 115 | void setup_opensil(void) |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 116 | { |
| 117 | const SIL_STATUS debug_ret = SilDebugSetup(HostDebugService); |
| 118 | SIL_STATUS_report("SilDebugSetup", debug_ret); |
| 119 | const size_t mem_req = xSimQueryMemoryRequirements(); |
| 120 | void *buf = cbmem_add(CBMEM_ID_AMD_OPENSIL, mem_req); |
| 121 | assert(buf); |
| 122 | /* We run all openSIL timepoints in the same stage so using TP1 as argument is fine. */ |
| 123 | const SIL_STATUS assign_mem_ret = xSimAssignMemoryTp1(buf, mem_req); |
| 124 | SIL_STATUS_report("xSimAssignMemory", assign_mem_ret); |
Arthur Heymans | 81ceea1 | 2023-07-14 19:56:03 +0200 | [diff] [blame] | 125 | |
| 126 | setup_rc_manager_default(); |
Martin Roth | f643a4d | 2023-09-27 16:46:46 -0600 | [diff] [blame] | 127 | configure_usb(); |
Arthur Heymans | 62389ab | 2023-07-14 20:11:15 +0200 | [diff] [blame] | 128 | configure_sata(); |
Felix Held | e5197e1 | 2024-01-22 18:17:57 +0100 | [diff] [blame] | 129 | configure_mpio(); |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 130 | } |
| 131 | |
Felix Held | dc12a38 | 2024-01-16 00:50:46 +0100 | [diff] [blame^] | 132 | void opensil_entry(SIL_TIMEPOINT timepoint) |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 133 | { |
| 134 | SIL_STATUS ret; |
| 135 | SIL_TIMEPOINT tp = (uintptr_t)timepoint; |
| 136 | |
| 137 | switch (tp) { |
| 138 | case SIL_TP1: |
| 139 | ret = InitializeSiTp1(); |
| 140 | break; |
| 141 | case SIL_TP2: |
| 142 | ret = InitializeSiTp2(); |
| 143 | break; |
| 144 | case SIL_TP3: |
| 145 | ret = InitializeSiTp3(); |
| 146 | break; |
| 147 | default: |
Felix Held | c7be078 | 2023-12-13 23:09:48 +0100 | [diff] [blame] | 148 | printk(BIOS_ERR, "Unknown openSIL timepoint\n"); |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 149 | return; |
| 150 | } |
| 151 | char opensil_function[16]; |
| 152 | snprintf(opensil_function, sizeof(opensil_function), "InitializeSiTp%d", tp); |
| 153 | SIL_STATUS_report(opensil_function, ret); |
| 154 | if (ret == SilResetRequestColdImm || ret == SilResetRequestColdDef) { |
Felix Held | c7be078 | 2023-12-13 23:09:48 +0100 | [diff] [blame] | 155 | printk(BIOS_INFO, "openSIL requested a cold reset"); |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 156 | do_cold_reset(); |
| 157 | } else if (ret == SilResetRequestWarmImm || ret == SilResetRequestWarmDef) { |
Felix Held | c7be078 | 2023-12-13 23:09:48 +0100 | [diff] [blame] | 158 | printk(BIOS_INFO, "openSIL requested a warm reset"); |
Arthur Heymans | adee6a6 | 2023-07-14 19:42:40 +0200 | [diff] [blame] | 159 | do_warm_reset(); |
| 160 | } |
| 161 | } |
| 162 | |
Felix Held | dc12a38 | 2024-01-16 00:50:46 +0100 | [diff] [blame^] | 163 | /* TODO: also call timepoints 2 and 3 from coreboot. Are they NOOP? */ |