Felix Singer | d959a20 | 2018-09-17 01:26:51 +0200 | [diff] [blame^] | 1 | # SPDX-License-Identifier: GPL-2.0-only |
| 2 | |
| 3 | chip soc/intel/skylake |
| 4 | register "gpu_pp_up_delay_ms" = "200" # T3 |
| 5 | register "gpu_pp_down_delay_ms" = " 0" # T10 |
| 6 | register "gpu_pp_cycle_delay_ms" = "500" # T12 |
| 7 | register "gpu_pp_backlight_on_delay_ms" = " 50" # T7 |
| 8 | register "gpu_pp_backlight_off_delay_ms" = " 0" # T9 |
| 9 | |
| 10 | register "gpu_pch_backlight_pwm_hz" = "200" |
| 11 | |
| 12 | # IGD Displays |
| 13 | register "gfx" = "GMA_STATIC_DISPLAYS(0)" |
| 14 | |
| 15 | # FSP Configuration |
| 16 | register "SkipExtGfxScan" = "1" |
| 17 | register "SaGv" = "SaGv_Enabled" |
| 18 | register "eist_enable" = "1" |
| 19 | |
| 20 | register "PmConfigSlpS3MinAssert" = "2" # 50ms |
| 21 | register "PmConfigSlpS4MinAssert" = "1" # 1s |
| 22 | register "PmConfigSlpSusMinAssert" = "3" # 500ms |
| 23 | register "PmConfigSlpAMinAssert" = "3" # 2s |
| 24 | |
| 25 | # Send an extra VR mailbox command for the PS4 exit issue |
| 26 | register "SendVrMbxCmd" = "2" |
| 27 | |
| 28 | register "power_limits_config" = "{ |
| 29 | .tdp_pl1_override = 20, |
| 30 | .tdp_pl2_override = 30, |
| 31 | }" |
| 32 | |
| 33 | register "common_soc_config" = "{ |
| 34 | .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, |
| 35 | }" |
| 36 | |
| 37 | register "SerialIoDevMode" = "{ |
| 38 | [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART |
| 39 | }" |
| 40 | |
| 41 | device cpu_cluster 0 on |
| 42 | device lapic 0 on end |
| 43 | end |
| 44 | device domain 0 on |
| 45 | subsystemid 0x1558 0x1313 inherit |
| 46 | device pci 00.0 on end # Host Bridge |
| 47 | device pci 02.0 on end # Integrated Graphics Device |
| 48 | device pci 04.0 on end # SA thermal subsystem |
| 49 | device pci 05.0 off end # Imaging Unit |
| 50 | device pci 08.0 on end # Gaussian Mixture Model |
| 51 | device pci 13.0 off end # Sensor Hub |
| 52 | device pci 14.0 on # USB xHCI |
| 53 | register "SsicPortEnable" = "0" |
| 54 | # USB2 |
| 55 | register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A, right |
| 56 | register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE |
| 57 | register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right |
| 58 | register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera |
| 59 | register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth |
| 60 | register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A, left |
| 61 | register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C, right |
| 62 | # USB3 |
| 63 | register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, right |
| 64 | register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G |
| 65 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C, right |
| 66 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A, left |
| 67 | end |
| 68 | device pci 14.1 off end # USB xDCI (OTG) |
| 69 | device pci 14.2 on end # Thermal Subsystem |
| 70 | device pci 14.3 off end # Camera |
| 71 | device pci 15.0 off end # I2C0 |
| 72 | device pci 15.1 off end # I2C1 |
| 73 | device pci 15.2 off end # I2C2 |
| 74 | device pci 15.3 off end # I2C3 |
| 75 | device pci 16.0 on # Management Engine Interface 1 |
| 76 | register "HeciEnabled" = "1" |
| 77 | end |
| 78 | device pci 16.1 off end # Management Engine Interface 2 |
| 79 | device pci 16.2 off end # Management Engine IDE-R |
| 80 | device pci 16.3 off end # Management Engine KT Redirection |
| 81 | device pci 16.4 off end # Management Engine Interface 3 |
| 82 | device pci 17.0 on # SATA |
| 83 | register "SataMode" = "KBLFSP_SATA_MODE_AHCI" |
| 84 | register "SataSalpSupport" = "0" |
| 85 | # Ports |
| 86 | register "SataPortsEnable[0]" = "1" |
| 87 | register "SataPortsEnable[2]" = "1" |
| 88 | register "SataPortsDevSlp[2]" = "1" |
| 89 | end |
| 90 | device pci 19.0 on end # UART 2 |
| 91 | device pci 19.1 off end # I2C5 |
| 92 | device pci 19.2 off end # I2C4 |
| 93 | device pci 1c.0 on # PCI Express Port 1 |
| 94 | device pci 00.0 on end # x4 TBT |
| 95 | register "PcieRpEnable[0]" = "1" |
| 96 | register "PcieRpClkReqSupport[0]" = "1" |
| 97 | register "PcieRpClkReqNumber[0]" = "4" |
| 98 | register "PcieRpClkSrcNumber[0]" = "4" |
| 99 | register "PcieRpHotPlug[0]" = "1" |
| 100 | register "PcieRpLtrEnable[0]" = "1" |
| 101 | smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthOther" "Thunderbolt/Type-C" "SlotDataBusWidth4X" |
| 102 | end |
| 103 | device pci 1c.1 off end # PCI Express Port 2 |
| 104 | device pci 1c.2 off end # PCI Express Port 3 |
| 105 | device pci 1c.3 off end # PCI Express Port 4 |
| 106 | device pci 1c.4 on # PCI Express Port 5 |
| 107 | device pci 00.0 on end # x1 LAN |
| 108 | register "PcieRpEnable[4]" = "1" |
| 109 | register "PcieRpClkReqSupport[4]" = "1" |
| 110 | register "PcieRpClkReqNumber[4]" = "3" |
| 111 | register "PcieRpClkSrcNumber[4]" = "3" |
| 112 | register "PcieRpLtrEnable[4]" = "1" |
| 113 | end |
| 114 | device pci 1c.5 on # PCI Express Port 6 |
| 115 | device pci 00.0 on end # x1 WLAN |
| 116 | register "PcieRpEnable[5]" = "1" |
| 117 | register "PcieRpClkReqSupport[5]" = "1" |
| 118 | register "PcieRpClkReqNumber[5]" = "2" |
| 119 | register "PcieRpClkSrcNumber[5]" = "2" |
| 120 | register "PcieRpLtrEnable[5]" = "1" |
| 121 | smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/A/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" |
| 122 | end |
| 123 | device pci 1c.6 off end # PCI Express Port 7 |
| 124 | device pci 1c.7 off end # PCI Express Port 8 |
| 125 | device pci 1d.0 on # PCI Express Port 9 |
| 126 | device pci 00.0 on end # x4 M.2/M (J_SSD1) |
| 127 | register "PcieRpEnable[8]" = "1" |
| 128 | register "PcieRpClkReqSupport[8]" = "1" |
| 129 | register "PcieRpClkReqNumber[8]" = "5" |
| 130 | register "PcieRpClkSrcNumber[8]" = "5" |
| 131 | register "PcieRpLtrEnable[8]" = "1" |
| 132 | smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" |
| 133 | end |
| 134 | device pci 1d.1 off end # PCI Express Port 10 |
| 135 | device pci 1d.2 off end # PCI Express Port 11 |
| 136 | device pci 1d.3 off end # PCI Express Port 12 |
| 137 | device pci 1e.0 off end # UART 0 |
| 138 | device pci 1e.1 off end # UART 1 |
| 139 | device pci 1e.2 off end # GSPI 0 |
| 140 | device pci 1e.3 off end # GSPI 1 |
| 141 | device pci 1e.4 off end # eMMC |
| 142 | device pci 1e.5 off end # SDIO |
| 143 | device pci 1e.6 off end # SDXC |
| 144 | device pci 1f.0 on # LPC Interface |
| 145 | register "gen1_dec" = "0x000c0681" |
| 146 | register "gen2_dec" = "0x000c1641" |
| 147 | register "gen3_dec" = "0x000c0081" |
| 148 | register "gen4_dec" = "0x00040069" |
| 149 | register "serirq_mode" = "SERIRQ_CONTINUOUS" |
| 150 | chip drivers/pc80/tpm |
| 151 | device pnp 0c31.0 on end |
| 152 | end |
| 153 | end |
| 154 | device pci 1f.1 hidden end # P2SB |
| 155 | device pci 1f.2 on # Power Management Controller |
| 156 | register "gpe0_dw0" = "GPP_C" |
| 157 | register "gpe0_dw1" = "GPP_D" |
| 158 | register "gpe0_dw2" = "GPP_E" |
| 159 | end |
| 160 | device pci 1f.3 on end # Intel HDA |
| 161 | device pci 1f.4 on end # SMBus |
| 162 | device pci 1f.5 on end # PCH SPI |
| 163 | device pci 1f.6 off end # GbE |
| 164 | device pci 1f.7 off end # Trace Hub |
| 165 | end |
| 166 | end |