Dtrain Hsu | 1017a8f | 2022-04-28 14:28:54 +0800 | [diff] [blame] | 1 | fw_config |
| 2 | field DB_DISPLAY 0 3 |
| 3 | option DB_ABSENT 0 |
| 4 | option DB_HDMI 1 |
| 5 | option DB_DP 2 |
| 6 | end |
| 7 | end |
| 8 | |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 9 | chip soc/intel/alderlake |
Dtrain Hsu | 230cdcf | 2022-06-23 17:01:47 +0800 | [diff] [blame] | 10 | register "sagv" = "SaGv_Enabled" |
| 11 | |
Ian Feng | d36aca5 | 2022-06-16 15:17:06 +0800 | [diff] [blame] | 12 | # GPE configuration |
| 13 | register "pmc_gpe0_dw1" = "GPP_H" |
| 14 | |
Dtrain Hsu | f5ead3f | 2022-11-04 11:57:23 +0800 | [diff] [blame] | 15 | # As per Intel Advisory doc#723158, the change is required to prevent possible |
| 16 | # display flickering issue. |
| 17 | register "usb2_phy_sus_pg_disable" = "1" |
| 18 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 19 | # Intel Common SoC Config |
| 20 | #+-------------------+---------------------------+ |
| 21 | #| Field | Value | |
| 22 | #+-------------------+---------------------------+ |
| 23 | #| I2C0 | Audio | |
| 24 | #| I2C1 | cr50 TPM. Early init is | |
| 25 | #| | required to set up a BAR | |
| 26 | #| | for TPM communication | |
| 27 | #+-------------------+---------------------------+ |
| 28 | register "common_soc_config" = "{ |
| 29 | .i2c[0] = { |
| 30 | .speed = I2C_SPEED_FAST, |
| 31 | }, |
| 32 | .i2c[1] = { |
| 33 | .early_init = 1, |
| 34 | .speed = I2C_SPEED_FAST, |
| 35 | }, |
| 36 | }" |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 37 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 38 | register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 |
| 39 | register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable Port 2 |
| 40 | register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3 |
| 41 | register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4 |
| 42 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 43 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 44 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Rear USB Type A |
| 45 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB HUB |
| 46 | |
Dtrain Hsu | d8358ee | 2023-03-09 16:31:38 +0800 | [diff] [blame^] | 47 | # Bitmap for Wake Enable on USB attach/detach |
| 48 | register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ |
| 49 | USB_PORT_WAKE_ENABLE(6) | \ |
| 50 | USB_PORT_WAKE_ENABLE(7) | \ |
| 51 | USB_PORT_WAKE_ENABLE(8) | \ |
| 52 | USB_PORT_WAKE_ENABLE(9)" |
| 53 | register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) | \ |
| 54 | USB_PORT_WAKE_ENABLE(2) | \ |
| 55 | USB_PORT_WAKE_ENABLE(3) | \ |
| 56 | USB_PORT_WAKE_ENABLE(4)" |
| 57 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 58 | register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # BTB |
| 59 | register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 |
| 60 | |
| 61 | # I2C Port Config |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 62 | register "serial_io_i2c_mode" = "{ |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 63 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 64 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 65 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 66 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 67 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 68 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 69 | }" |
| 70 | |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 71 | register "serial_io_gspi_mode" = "{ |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 72 | [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
| 73 | [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| 74 | }" |
| 75 | |
Dtrain Hsu | 035e319 | 2022-06-23 15:02:11 +0800 | [diff] [blame] | 76 | register "ddi_ports_config" = "{ |
| 77 | [DDI_PORT_A] = DDI_ENABLE_HPD, |
| 78 | [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, |
| 79 | [DDI_PORT_1] = DDI_ENABLE_HPD, |
| 80 | [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC |
| 81 | }" |
| 82 | |
Dtrain Hsu | b1d26b4 | 2022-07-07 16:11:41 +0800 | [diff] [blame] | 83 | register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ |
| 84 | .tdp_pl1_override = 30, |
| 85 | }" |
| 86 | |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 87 | register "tcc_offset" = "6" |
| 88 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 89 | device domain 0 on |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 90 | device ref dtt on |
| 91 | chip drivers/intel/dptf |
| 92 | ## sensor information |
| 93 | register "options.tsr[0].desc" = ""DRAM_SOC"" |
| 94 | register "options.tsr[1].desc" = ""Ambient"" |
| 95 | register "options.tsr[2].desc" = ""Charger"" |
| 96 | register "options.tsr[3].desc" = ""WWAN"" |
| 97 | |
| 98 | # TODO: below values are initial reference values only |
| 99 | ## Active Policy |
| 100 | register "policies.active" = "{ |
| 101 | [0] = { |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 102 | .target = DPTF_TEMP_SENSOR_0, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 103 | .thresholds = { |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 104 | TEMP_PCT(90, 97), |
| 105 | TEMP_PCT(60, 80), |
| 106 | TEMP_PCT(55, 70), |
| 107 | TEMP_PCT(50, 64), |
| 108 | TEMP_PCT(45, 54), |
| 109 | TEMP_PCT(42, 47), |
| 110 | TEMP_PCT(38, 43), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 111 | TEMP_PCT(35, 40), |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 112 | TEMP_PCT(33, 36), |
| 113 | TEMP_PCT(30, 32), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 114 | } |
| 115 | }, |
| 116 | [1] = { |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 117 | .target = DPTF_TEMP_SENSOR_1, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 118 | .thresholds = { |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 119 | TEMP_PCT(90, 97), |
| 120 | TEMP_PCT(60, 80), |
| 121 | TEMP_PCT(55, 70), |
| 122 | TEMP_PCT(50, 64), |
| 123 | TEMP_PCT(45, 54), |
| 124 | TEMP_PCT(42, 47), |
| 125 | TEMP_PCT(38, 43), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 126 | TEMP_PCT(35, 40), |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 127 | TEMP_PCT(33, 36), |
| 128 | TEMP_PCT(30, 32), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 129 | } |
| 130 | }, |
| 131 | [2] = { |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 132 | .target = DPTF_TEMP_SENSOR_2, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 133 | .thresholds = { |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 134 | TEMP_PCT(90, 97), |
| 135 | TEMP_PCT(60, 80), |
| 136 | TEMP_PCT(55, 70), |
| 137 | TEMP_PCT(50, 64), |
| 138 | TEMP_PCT(45, 54), |
| 139 | TEMP_PCT(42, 47), |
| 140 | TEMP_PCT(38, 43), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 141 | TEMP_PCT(35, 40), |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 142 | TEMP_PCT(33, 36), |
| 143 | TEMP_PCT(30, 32), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 144 | } |
| 145 | }, |
| 146 | [3] = { |
Dtrain Hsu | 8dd47ae | 2022-05-27 17:05:34 +0800 | [diff] [blame] | 147 | .target = DPTF_TEMP_SENSOR_3, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 148 | .thresholds = { |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 149 | TEMP_PCT(90, 97), |
| 150 | TEMP_PCT(60, 80), |
| 151 | TEMP_PCT(55, 70), |
| 152 | TEMP_PCT(50, 64), |
| 153 | TEMP_PCT(45, 54), |
| 154 | TEMP_PCT(42, 47), |
| 155 | TEMP_PCT(38, 43), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 156 | TEMP_PCT(35, 40), |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 157 | TEMP_PCT(33, 36), |
| 158 | TEMP_PCT(30, 32), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 159 | } |
| 160 | } |
| 161 | }" |
| 162 | |
| 163 | ## Passive Policy |
| 164 | register "policies.passive" = "{ |
| 165 | [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), |
| 166 | [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 10000), |
| 167 | [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 10000), |
| 168 | [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 10000), |
| 169 | [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 10000), |
| 170 | }" |
| 171 | |
| 172 | ## Critical Policy |
| 173 | register "policies.critical" = "{ |
| 174 | [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), |
Dtrain Hsu | 7afa1ba | 2022-09-02 16:33:32 +0800 | [diff] [blame] | 175 | [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 97, SHUTDOWN), |
| 176 | [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 97, SHUTDOWN), |
| 177 | [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 97, SHUTDOWN), |
| 178 | [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 97, SHUTDOWN), |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 179 | }" |
| 180 | |
| 181 | register "controls.power_limits" = "{ |
| 182 | .pl1 = { |
Dtrain Hsu | 79df32d | 2022-05-23 17:43:07 +0800 | [diff] [blame] | 183 | .min_power = 12000, |
| 184 | .max_power = 25000, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 185 | .time_window_min = 28 * MSECS_PER_SEC, |
| 186 | .time_window_max = 28 * MSECS_PER_SEC, |
| 187 | .granularity = 500, |
| 188 | }, |
| 189 | .pl2 = { |
| 190 | .min_power = 39000, |
| 191 | .max_power = 39000, |
| 192 | .time_window_min = 28 * MSECS_PER_SEC, |
| 193 | .time_window_max = 32 * MSECS_PER_SEC, |
| 194 | .granularity = 1000, |
| 195 | } |
| 196 | }" |
| 197 | |
Dtrain Hsu | 6aadb93 | 2022-06-20 16:54:13 +0800 | [diff] [blame] | 198 | register "oem_data.oem_variables" = "{ |
| 199 | [0] = 0x0 |
| 200 | }" |
| 201 | |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 202 | ## Charger Performance Control (Control, mA) |
| 203 | register "controls.charger_perf" = "{ |
| 204 | [0] = { 255, 1700 }, |
| 205 | [1] = { 24, 1500 }, |
| 206 | [2] = { 16, 1000 }, |
| 207 | [3] = { 8, 500 } |
| 208 | }" |
| 209 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
| 210 | register "controls.fan_perf" = "{ |
Dtrain Hsu | ed688ab | 2022-09-02 10:42:13 +0800 | [diff] [blame] | 211 | [0] = { 100, 6060, 0, 0, }, |
| 212 | [1] = { 90, 5585, 0, 0, }, |
| 213 | [2] = { 80, 4964, 0, 0, }, |
| 214 | [3] = { 70, 4237, 0, 0, }, |
| 215 | [4] = { 64, 3963, 0, 0, }, |
| 216 | [5] = { 60, 3510, 0, 0, }, |
| 217 | [6] = { 54, 3212, 0, 0, }, |
| 218 | [7] = { 50, 2808, 0, 0, }, |
| 219 | [8] = { 48, 2776, 0, 0, }, |
| 220 | [9] = { 47, 2715, 0, 0, }, |
| 221 | [10] = { 45, 2566, 0, 0, }, |
| 222 | [11] = { 43, 2415, 0, 0, }, |
| 223 | [12] = { 40, 2010, 0, 0, }, |
| 224 | [13] = { 36, 1813, 0, 0, }, |
| 225 | [14] = { 35, 1686, 0, 0, }, |
| 226 | [15] = { 32, 1404, 0, 0, }, |
| 227 | [16] = { 30, 1160, 0, 0, }, |
| 228 | [17] = { 20, 760, 0, 0, }, |
| 229 | [18] = { 10, 760, 0, 0, }, |
| 230 | [19] = { 0, 0, 0, 0, } |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 231 | }" |
| 232 | |
| 233 | ## Fan options |
| 234 | register "options.fan.fine_grained_control" = "1" |
| 235 | register "options.fan.step_size" = "2" |
| 236 | |
| 237 | device generic 0 alias dptf_policy on end |
| 238 | end |
| 239 | end |
Ian Feng | d36aca5 | 2022-06-16 15:17:06 +0800 | [diff] [blame] | 240 | device ref pcie_rp5 on |
| 241 | # Enable WLAN PCIE 5 using clk 2 |
| 242 | register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| 243 | .clk_src = 2, |
| 244 | .clk_req = 2, |
| 245 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 246 | }" |
| 247 | chip drivers/wifi/generic |
| 248 | register "wake" = "GPE0_DW1_03" |
Kapil Porwal | f90ceb4 | 2022-12-02 17:59:48 +0530 | [diff] [blame] | 249 | register "add_acpi_dma_property" = "true" |
Ian Feng | d36aca5 | 2022-06-16 15:17:06 +0800 | [diff] [blame] | 250 | device pci 00.0 on end |
| 251 | end |
| 252 | chip soc/intel/common/block/pcie/rtd3 |
| 253 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" |
| 254 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H20)" |
| 255 | register "srcclk_pin" = "2" |
| 256 | device generic 0 on end |
| 257 | end |
| 258 | end |
Dtrain Hsu | 335edc0 | 2022-03-07 13:42:03 +0800 | [diff] [blame] | 259 | device ref pcie_rp6 on |
| 260 | # Enable PCIe-to-eMMC bridge PCIE 6 using clk 1 |
| 261 | register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| 262 | .clk_src = 1, |
| 263 | .clk_req = 1, |
| 264 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 265 | }" |
| 266 | chip soc/intel/common/block/pcie/rtd3 |
| 267 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" |
| 268 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" |
| 269 | register "srcclk_pin" = "1" |
Dtrain Hsu | 850925f | 2022-05-26 16:36:52 +0800 | [diff] [blame] | 270 | register "reset_delay_ms" = "50" |
| 271 | register "enable_delay_ms" = "20" |
Dtrain Hsu | 335edc0 | 2022-03-07 13:42:03 +0800 | [diff] [blame] | 272 | device generic 0 alias emmc_rtd3 on end |
| 273 | end |
| 274 | end # BH799BBLN |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 275 | device ref pcie_rp7 on |
| 276 | chip drivers/net |
| 277 | register "customized_leds" = "0x05af" |
| 278 | register "wake" = "GPE0_DW0_07" #GPP_A7 |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 279 | register "device_index" = "0" |
Kapil Porwal | 39f5042 | 2022-11-26 02:38:38 +0530 | [diff] [blame] | 280 | register "add_acpi_dma_property" = "true" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 281 | device pci 00.0 on end |
| 282 | end |
| 283 | end # RTL8111K Ethernet NIC |
| 284 | device ref pcie_rp8 off end |
| 285 | device ref pcie_rp9 off end |
| 286 | |
| 287 | device ref pcie4_0 on |
| 288 | # Enable CPU PCIE RP 1 using CLK 0 |
| 289 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 290 | .clk_req = 0, |
| 291 | .clk_src = 0, |
| 292 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 293 | }" |
| 294 | end |
| 295 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 296 | device ref cnvi_wifi on |
| 297 | chip drivers/wifi/generic |
| 298 | register "wake" = "GPE0_PME_B0" |
| 299 | device generic 0 on end |
| 300 | end |
| 301 | end |
| 302 | |
Dtrain Hsu | 7886d46 | 2022-05-06 13:24:11 +0800 | [diff] [blame] | 303 | device ref tbt_pcie_rp0 off end |
| 304 | device ref tbt_pcie_rp1 off end |
| 305 | device ref tbt_pcie_rp2 off end |
| 306 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 307 | device ref tcss_dma0 off end |
| 308 | device ref tcss_dma1 off end |
| 309 | |
| 310 | device ref i2c0 on |
| 311 | chip drivers/i2c/generic |
| 312 | register "hid" = ""RTL5682"" |
| 313 | register "name" = ""RT58"" |
| 314 | register "desc" = ""Headset Codec"" |
| 315 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" |
| 316 | # Set the jd_src to RT5668_JD1 for jack detection |
| 317 | register "property_count" = "1" |
| 318 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 319 | register "property_list[0].name" = ""realtek,jd-src"" |
| 320 | register "property_list[0].integer" = "1" |
| 321 | device i2c 1a on end |
| 322 | end |
| 323 | end #I2C0 |
| 324 | device ref gspi1 off end |
| 325 | device ref pch_espi on |
| 326 | chip ec/google/chromeec |
| 327 | use conn0 as mux_conn[0] |
| 328 | device pnp 0c09.0 on end |
| 329 | end |
| 330 | end |
| 331 | device ref pmc hidden |
| 332 | chip drivers/intel/pmc_mux |
| 333 | device generic 0 on |
| 334 | chip drivers/intel/pmc_mux/conn |
| 335 | use usb2_port1 as usb2_port |
| 336 | use tcss_usb3_port1 as usb3_port |
| 337 | device generic 0 alias conn0 on end |
| 338 | end |
| 339 | end |
| 340 | end |
| 341 | end |
| 342 | device ref tcss_xhci on |
| 343 | chip drivers/usb/acpi |
| 344 | device ref tcss_root_hub on |
| 345 | chip drivers/usb/acpi |
| 346 | register "desc" = ""USB3 Type-C Port C0 (MLB)"" |
| 347 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 348 | register "use_custom_pld" = "true" |
| 349 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 350 | "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" |
Ron Lee | 558952a | 2022-12-13 19:48:59 +0800 | [diff] [blame] | 351 | register "usb_lpm_incapable" = "true" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 352 | device ref tcss_usb3_port1 on end |
| 353 | end |
| 354 | end |
| 355 | end |
| 356 | end |
| 357 | device ref xhci on |
| 358 | chip drivers/usb/acpi |
| 359 | device ref xhci_root_hub on |
| 360 | chip drivers/usb/acpi |
| 361 | register "desc" = ""USB2 Type-C Port C0 (MLB)"" |
| 362 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 363 | register "use_custom_pld" = "true" |
| 364 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 365 | "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 366 | device ref usb2_port1 on end |
| 367 | end |
| 368 | chip drivers/usb/acpi |
| 369 | register "desc" = ""USB2 Hub"" |
| 370 | register "type" = "UPC_TYPE_A" |
| 371 | register "use_custom_pld" = "true" |
| 372 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 373 | "ACPI_PLD_TYPE_A(BACK, RIGHT, ACPI_PLD_GROUP(5, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 374 | device ref usb2_port6 on end |
| 375 | end |
| 376 | chip drivers/usb/acpi |
| 377 | register "desc" = ""USB2 Type-A Port A2 (MLB)"" |
| 378 | register "type" = "UPC_TYPE_A" |
| 379 | register "use_custom_pld" = "true" |
| 380 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 381 | "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 382 | device ref usb2_port7 on end |
| 383 | end |
| 384 | chip drivers/usb/acpi |
| 385 | register "desc" = ""USB2 Type-A Port A1 (MLB)"" |
| 386 | register "type" = "UPC_TYPE_A" |
| 387 | register "use_custom_pld" = "true" |
| 388 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 389 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(4, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 390 | device ref usb2_port8 on end |
| 391 | end |
| 392 | chip drivers/usb/acpi |
| 393 | register "desc" = ""USB2 Type-A Port A0 (MLB)"" |
| 394 | register "type" = "UPC_TYPE_A" |
| 395 | register "use_custom_pld" = "true" |
| 396 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 397 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 398 | device ref usb2_port9 on end |
| 399 | end |
| 400 | chip drivers/usb/acpi |
| 401 | register "desc" = ""USB2 Bluetooth"" |
| 402 | register "type" = "UPC_TYPE_INTERNAL" |
| 403 | register "reset_gpio" = |
| 404 | "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" |
| 405 | device ref usb2_port10 on end |
| 406 | end |
| 407 | chip drivers/usb/acpi |
| 408 | register "desc" = ""USB3 Type-A Port A0 (MLB)"" |
| 409 | register "type" = "UPC_TYPE_USB3_A" |
| 410 | register "use_custom_pld" = "true" |
| 411 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 412 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 413 | device ref usb3_port1 on end |
| 414 | end |
| 415 | chip drivers/usb/acpi |
| 416 | register "desc" = ""USB3 Type-A Port A1 (MLB)"" |
| 417 | register "type" = "UPC_TYPE_USB3_A" |
| 418 | register "use_custom_pld" = "true" |
| 419 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 420 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(4, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 421 | device ref usb3_port2 on end |
| 422 | end |
| 423 | chip drivers/usb/acpi |
| 424 | register "desc" = ""USB3 Type-A Port A2 (MLB)"" |
| 425 | register "type" = "UPC_TYPE_USB3_A" |
| 426 | register "use_custom_pld" = "true" |
| 427 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 428 | "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 429 | device ref usb3_port3 on end |
| 430 | end |
| 431 | chip drivers/usb/acpi |
| 432 | register "desc" = ""USB Hub"" |
| 433 | register "type" = "UPC_TYPE_USB3_A" |
| 434 | register "use_custom_pld" = "true" |
| 435 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 436 | "ACPI_PLD_TYPE_A(BACK, RIGHT, ACPI_PLD_GROUP(5, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 437 | device ref usb3_port4 on end |
| 438 | end |
| 439 | end |
| 440 | end |
| 441 | end |
| 442 | end |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 443 | end |