Dtrain Hsu | 1017a8f | 2022-04-28 14:28:54 +0800 | [diff] [blame^] | 1 | fw_config |
| 2 | field DB_DISPLAY 0 3 |
| 3 | option DB_ABSENT 0 |
| 4 | option DB_HDMI 1 |
| 5 | option DB_DP 2 |
| 6 | end |
| 7 | end |
| 8 | |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 9 | chip soc/intel/alderlake |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 10 | # Intel Common SoC Config |
| 11 | #+-------------------+---------------------------+ |
| 12 | #| Field | Value | |
| 13 | #+-------------------+---------------------------+ |
| 14 | #| I2C0 | Audio | |
| 15 | #| I2C1 | cr50 TPM. Early init is | |
| 16 | #| | required to set up a BAR | |
| 17 | #| | for TPM communication | |
| 18 | #+-------------------+---------------------------+ |
| 19 | register "common_soc_config" = "{ |
| 20 | .i2c[0] = { |
| 21 | .speed = I2C_SPEED_FAST, |
| 22 | }, |
| 23 | .i2c[1] = { |
| 24 | .early_init = 1, |
| 25 | .speed = I2C_SPEED_FAST, |
| 26 | }, |
| 27 | }" |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 28 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 29 | register "usb2_ports[1]" = "USB2_PORT_EMPTY" # Disable Port 1 |
| 30 | register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable Port 2 |
| 31 | register "usb2_ports[3]" = "USB2_PORT_EMPTY" # Disable Port 3 |
| 32 | register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable Port 4 |
| 33 | register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 34 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 35 | register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Rear USB Type A |
| 36 | register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB HUB |
| 37 | |
| 38 | register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC1)" # BTB |
| 39 | register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 |
| 40 | |
| 41 | # I2C Port Config |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 42 | register "serial_io_i2c_mode" = "{ |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 43 | [PchSerialIoIndexI2C0] = PchSerialIoPci, |
| 44 | [PchSerialIoIndexI2C1] = PchSerialIoPci, |
| 45 | [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| 46 | [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| 47 | [PchSerialIoIndexI2C4] = PchSerialIoDisabled, |
| 48 | [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| 49 | }" |
| 50 | |
MAULIK V VAGHELA | 215a97e | 2022-03-07 18:39:17 +0530 | [diff] [blame] | 51 | register "serial_io_gspi_mode" = "{ |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 52 | [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, |
| 53 | [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, |
| 54 | }" |
| 55 | |
| 56 | device domain 0 on |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 57 | device ref dtt on |
| 58 | chip drivers/intel/dptf |
| 59 | ## sensor information |
| 60 | register "options.tsr[0].desc" = ""DRAM_SOC"" |
| 61 | register "options.tsr[1].desc" = ""Ambient"" |
| 62 | register "options.tsr[2].desc" = ""Charger"" |
| 63 | register "options.tsr[3].desc" = ""WWAN"" |
| 64 | |
| 65 | # TODO: below values are initial reference values only |
| 66 | ## Active Policy |
| 67 | register "policies.active" = "{ |
| 68 | [0] = { |
| 69 | .target = DPTF_CPU, |
| 70 | .thresholds = { |
| 71 | TEMP_PCT(80, 97), |
| 72 | TEMP_PCT(65, 93), |
| 73 | TEMP_PCT(58, 86), |
| 74 | TEMP_PCT(50, 80), |
| 75 | TEMP_PCT(45, 64), |
| 76 | TEMP_PCT(43, 52), |
| 77 | TEMP_PCT(40, 47), |
| 78 | TEMP_PCT(35, 40), |
| 79 | } |
| 80 | }, |
| 81 | [1] = { |
Dtrain Hsu | 8dd47ae | 2022-05-27 17:05:34 +0800 | [diff] [blame] | 82 | .target = DPTF_TEMP_SENSOR_0, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 83 | .thresholds = { |
| 84 | TEMP_PCT(75, 97), |
| 85 | TEMP_PCT(70, 93), |
| 86 | TEMP_PCT(60, 86), |
| 87 | TEMP_PCT(52, 80), |
| 88 | TEMP_PCT(47, 64), |
| 89 | TEMP_PCT(43, 52), |
| 90 | TEMP_PCT(40, 47), |
| 91 | TEMP_PCT(35, 40), |
| 92 | } |
| 93 | }, |
| 94 | [2] = { |
Dtrain Hsu | 8dd47ae | 2022-05-27 17:05:34 +0800 | [diff] [blame] | 95 | .target = DPTF_TEMP_SENSOR_1, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 96 | .thresholds = { |
| 97 | TEMP_PCT(75, 97), |
| 98 | TEMP_PCT(70, 93), |
| 99 | TEMP_PCT(60, 86), |
| 100 | TEMP_PCT(52, 80), |
| 101 | TEMP_PCT(47, 64), |
| 102 | TEMP_PCT(43, 52), |
| 103 | TEMP_PCT(40, 47), |
| 104 | TEMP_PCT(35, 40), |
| 105 | } |
| 106 | }, |
| 107 | [3] = { |
Dtrain Hsu | 8dd47ae | 2022-05-27 17:05:34 +0800 | [diff] [blame] | 108 | .target = DPTF_TEMP_SENSOR_2, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 109 | .thresholds = { |
| 110 | TEMP_PCT(75, 97), |
| 111 | TEMP_PCT(70, 93), |
| 112 | TEMP_PCT(60, 86), |
| 113 | TEMP_PCT(52, 80), |
| 114 | TEMP_PCT(47, 64), |
| 115 | TEMP_PCT(43, 52), |
| 116 | TEMP_PCT(40, 47), |
| 117 | TEMP_PCT(35, 40), |
| 118 | } |
| 119 | }, |
| 120 | [4] = { |
Dtrain Hsu | 8dd47ae | 2022-05-27 17:05:34 +0800 | [diff] [blame] | 121 | .target = DPTF_TEMP_SENSOR_3, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 122 | .thresholds = { |
| 123 | TEMP_PCT(75, 97), |
| 124 | TEMP_PCT(70, 93), |
| 125 | TEMP_PCT(60, 86), |
| 126 | TEMP_PCT(52, 80), |
| 127 | TEMP_PCT(47, 64), |
| 128 | TEMP_PCT(43, 52), |
| 129 | TEMP_PCT(40, 47), |
| 130 | TEMP_PCT(35, 40), |
| 131 | } |
| 132 | } |
| 133 | }" |
| 134 | |
| 135 | ## Passive Policy |
| 136 | register "policies.passive" = "{ |
| 137 | [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000), |
| 138 | [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 90, 10000), |
| 139 | [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 90, 10000), |
| 140 | [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 90, 10000), |
| 141 | [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 90, 10000), |
| 142 | }" |
| 143 | |
| 144 | ## Critical Policy |
| 145 | register "policies.critical" = "{ |
| 146 | [0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN), |
| 147 | [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 93, SHUTDOWN), |
| 148 | [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 93, SHUTDOWN), |
| 149 | [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 93, SHUTDOWN), |
| 150 | [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 93, SHUTDOWN), |
| 151 | }" |
| 152 | |
| 153 | register "controls.power_limits" = "{ |
| 154 | .pl1 = { |
Dtrain Hsu | 79df32d | 2022-05-23 17:43:07 +0800 | [diff] [blame] | 155 | .min_power = 12000, |
| 156 | .max_power = 25000, |
Dtrain Hsu | 60260a5 | 2022-03-07 10:39:42 +0800 | [diff] [blame] | 157 | .time_window_min = 28 * MSECS_PER_SEC, |
| 158 | .time_window_max = 28 * MSECS_PER_SEC, |
| 159 | .granularity = 500, |
| 160 | }, |
| 161 | .pl2 = { |
| 162 | .min_power = 39000, |
| 163 | .max_power = 39000, |
| 164 | .time_window_min = 28 * MSECS_PER_SEC, |
| 165 | .time_window_max = 32 * MSECS_PER_SEC, |
| 166 | .granularity = 1000, |
| 167 | } |
| 168 | }" |
| 169 | |
| 170 | ## Charger Performance Control (Control, mA) |
| 171 | register "controls.charger_perf" = "{ |
| 172 | [0] = { 255, 1700 }, |
| 173 | [1] = { 24, 1500 }, |
| 174 | [2] = { 16, 1000 }, |
| 175 | [3] = { 8, 500 } |
| 176 | }" |
| 177 | ## Fan Performance Control (Percent, Speed, Noise, Power) |
| 178 | register "controls.fan_perf" = "{ |
| 179 | [0] = { 90, 6700, 220, 2200, }, |
| 180 | [1] = { 80, 5800, 180, 1800, }, |
| 181 | [2] = { 70, 5000, 145, 1450, }, |
| 182 | [3] = { 60, 4900, 115, 1150, }, |
| 183 | [4] = { 50, 3838, 90, 900, }, |
| 184 | [5] = { 40, 2904, 55, 550, }, |
| 185 | [6] = { 30, 2337, 30, 300, }, |
| 186 | [7] = { 20, 1608, 15, 150, }, |
| 187 | [8] = { 10, 800, 10, 100, }, |
| 188 | [9] = { 0, 0, 0, 50, } |
| 189 | }" |
| 190 | |
| 191 | ## Fan options |
| 192 | register "options.fan.fine_grained_control" = "1" |
| 193 | register "options.fan.step_size" = "2" |
| 194 | |
| 195 | device generic 0 alias dptf_policy on end |
| 196 | end |
| 197 | end |
Dtrain Hsu | 335edc0 | 2022-03-07 13:42:03 +0800 | [diff] [blame] | 198 | device ref pcie_rp6 on |
| 199 | # Enable PCIe-to-eMMC bridge PCIE 6 using clk 1 |
| 200 | register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| 201 | .clk_src = 1, |
| 202 | .clk_req = 1, |
| 203 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 204 | }" |
| 205 | chip soc/intel/common/block/pcie/rtd3 |
| 206 | register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" |
| 207 | register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D18)" |
| 208 | register "srcclk_pin" = "1" |
| 209 | device generic 0 alias emmc_rtd3 on end |
| 210 | end |
| 211 | end # BH799BBLN |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 212 | device ref pcie_rp7 on |
| 213 | chip drivers/net |
| 214 | register "customized_leds" = "0x05af" |
| 215 | register "wake" = "GPE0_DW0_07" #GPP_A7 |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 216 | register "device_index" = "0" |
| 217 | device pci 00.0 on end |
| 218 | end |
| 219 | end # RTL8111K Ethernet NIC |
| 220 | device ref pcie_rp8 off end |
| 221 | device ref pcie_rp9 off end |
| 222 | |
| 223 | device ref pcie4_0 on |
| 224 | # Enable CPU PCIE RP 1 using CLK 0 |
| 225 | register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| 226 | .clk_req = 0, |
| 227 | .clk_src = 0, |
| 228 | .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| 229 | }" |
| 230 | end |
| 231 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 232 | device ref cnvi_wifi on |
| 233 | chip drivers/wifi/generic |
| 234 | register "wake" = "GPE0_PME_B0" |
| 235 | device generic 0 on end |
| 236 | end |
| 237 | end |
| 238 | |
Dtrain Hsu | 7886d46 | 2022-05-06 13:24:11 +0800 | [diff] [blame] | 239 | device ref tbt_pcie_rp0 off end |
| 240 | device ref tbt_pcie_rp1 off end |
| 241 | device ref tbt_pcie_rp2 off end |
| 242 | |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 243 | device ref tcss_dma0 off end |
| 244 | device ref tcss_dma1 off end |
| 245 | |
| 246 | device ref i2c0 on |
| 247 | chip drivers/i2c/generic |
| 248 | register "hid" = ""RTL5682"" |
| 249 | register "name" = ""RT58"" |
| 250 | register "desc" = ""Headset Codec"" |
| 251 | register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" |
| 252 | # Set the jd_src to RT5668_JD1 for jack detection |
| 253 | register "property_count" = "1" |
| 254 | register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" |
| 255 | register "property_list[0].name" = ""realtek,jd-src"" |
| 256 | register "property_list[0].integer" = "1" |
| 257 | device i2c 1a on end |
| 258 | end |
| 259 | end #I2C0 |
| 260 | device ref gspi1 off end |
| 261 | device ref pch_espi on |
| 262 | chip ec/google/chromeec |
| 263 | use conn0 as mux_conn[0] |
| 264 | device pnp 0c09.0 on end |
| 265 | end |
| 266 | end |
| 267 | device ref pmc hidden |
| 268 | chip drivers/intel/pmc_mux |
| 269 | device generic 0 on |
| 270 | chip drivers/intel/pmc_mux/conn |
| 271 | use usb2_port1 as usb2_port |
| 272 | use tcss_usb3_port1 as usb3_port |
| 273 | device generic 0 alias conn0 on end |
| 274 | end |
| 275 | end |
| 276 | end |
| 277 | end |
| 278 | device ref tcss_xhci on |
| 279 | chip drivers/usb/acpi |
| 280 | device ref tcss_root_hub on |
| 281 | chip drivers/usb/acpi |
| 282 | register "desc" = ""USB3 Type-C Port C0 (MLB)"" |
| 283 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 284 | register "use_custom_pld" = "true" |
| 285 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 286 | "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 287 | device ref tcss_usb3_port1 on end |
| 288 | end |
| 289 | end |
| 290 | end |
| 291 | end |
| 292 | device ref xhci on |
| 293 | chip drivers/usb/acpi |
| 294 | device ref xhci_root_hub on |
| 295 | chip drivers/usb/acpi |
| 296 | register "desc" = ""USB2 Type-C Port C0 (MLB)"" |
| 297 | register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| 298 | register "use_custom_pld" = "true" |
| 299 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 300 | "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 301 | device ref usb2_port1 on end |
| 302 | end |
| 303 | chip drivers/usb/acpi |
| 304 | register "desc" = ""USB2 Hub"" |
| 305 | register "type" = "UPC_TYPE_A" |
| 306 | register "use_custom_pld" = "true" |
| 307 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 308 | "ACPI_PLD_TYPE_A(BACK, RIGHT, ACPI_PLD_GROUP(5, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 309 | device ref usb2_port6 on end |
| 310 | end |
| 311 | chip drivers/usb/acpi |
| 312 | register "desc" = ""USB2 Type-A Port A2 (MLB)"" |
| 313 | register "type" = "UPC_TYPE_A" |
| 314 | register "use_custom_pld" = "true" |
| 315 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 316 | "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 317 | device ref usb2_port7 on end |
| 318 | end |
| 319 | chip drivers/usb/acpi |
| 320 | register "desc" = ""USB2 Type-A Port A1 (MLB)"" |
| 321 | register "type" = "UPC_TYPE_A" |
| 322 | register "use_custom_pld" = "true" |
| 323 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 324 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(4, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 325 | device ref usb2_port8 on end |
| 326 | end |
| 327 | chip drivers/usb/acpi |
| 328 | register "desc" = ""USB2 Type-A Port A0 (MLB)"" |
| 329 | register "type" = "UPC_TYPE_A" |
| 330 | register "use_custom_pld" = "true" |
| 331 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 332 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 333 | device ref usb2_port9 on end |
| 334 | end |
| 335 | chip drivers/usb/acpi |
| 336 | register "desc" = ""USB2 Bluetooth"" |
| 337 | register "type" = "UPC_TYPE_INTERNAL" |
| 338 | register "reset_gpio" = |
| 339 | "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" |
| 340 | device ref usb2_port10 on end |
| 341 | end |
| 342 | chip drivers/usb/acpi |
| 343 | register "desc" = ""USB3 Type-A Port A0 (MLB)"" |
| 344 | register "type" = "UPC_TYPE_USB3_A" |
| 345 | register "use_custom_pld" = "true" |
| 346 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 347 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 348 | device ref usb3_port1 on end |
| 349 | end |
| 350 | chip drivers/usb/acpi |
| 351 | register "desc" = ""USB3 Type-A Port A1 (MLB)"" |
| 352 | register "type" = "UPC_TYPE_USB3_A" |
| 353 | register "use_custom_pld" = "true" |
| 354 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 355 | "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(4, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 356 | device ref usb3_port2 on end |
| 357 | end |
| 358 | chip drivers/usb/acpi |
| 359 | register "desc" = ""USB3 Type-A Port A2 (MLB)"" |
| 360 | register "type" = "UPC_TYPE_USB3_A" |
| 361 | register "use_custom_pld" = "true" |
| 362 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 363 | "ACPI_PLD_TYPE_A(BACK, LEFT, ACPI_PLD_GROUP(6, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 364 | device ref usb3_port3 on end |
| 365 | end |
| 366 | chip drivers/usb/acpi |
| 367 | register "desc" = ""USB Hub"" |
| 368 | register "type" = "UPC_TYPE_USB3_A" |
| 369 | register "use_custom_pld" = "true" |
| 370 | register "custom_pld" = |
Dtrain Hsu | 6b1c0e9 | 2022-05-23 16:38:31 +0800 | [diff] [blame] | 371 | "ACPI_PLD_TYPE_A(BACK, RIGHT, ACPI_PLD_GROUP(5, 1))" |
Dtrain Hsu | 4b80791 | 2022-03-03 13:41:59 +0800 | [diff] [blame] | 372 | device ref usb3_port4 on end |
| 373 | end |
| 374 | end |
| 375 | end |
| 376 | end |
| 377 | end |
Dtrain Hsu | e8c160e | 2022-02-10 10:32:27 +0800 | [diff] [blame] | 378 | end |