Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
Arthur Heymans | 0ab98d5 | 2022-04-07 19:14:48 +0200 | [diff] [blame] | 3 | #include "assert.h" |
Kyösti Mälkki | 84935f7 | 2021-01-11 20:13:34 +0200 | [diff] [blame] | 4 | #include <acpi/acpi_gnvs.h> |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 5 | #include <stddef.h> |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 6 | #include <stdint.h> |
| 7 | #include <string.h> |
| 8 | #include <rmodule.h> |
Raul E Rangel | c516098 | 2022-02-24 16:02:49 -0700 | [diff] [blame] | 9 | #include <cbmem.h> |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 10 | #include <cpu/x86/smm.h> |
| 11 | #include <commonlib/helpers.h> |
| 12 | #include <console/console.h> |
| 13 | #include <security/intel/stm/SmmStm.h> |
| 14 | |
| 15 | #define FXSAVE_SIZE 512 |
| 16 | #define SMM_CODE_SEGMENT_SIZE 0x10000 |
| 17 | /* FXSAVE area during relocation. While it may not be strictly needed the |
| 18 | SMM stub code relies on the FXSAVE area being non-zero to enable SSE |
| 19 | instructions within SMM mode. */ |
| 20 | static uint8_t fxsave_area_relocation[CONFIG_MAX_CPUS][FXSAVE_SIZE] |
| 21 | __attribute__((aligned(16))); |
| 22 | |
| 23 | /* |
| 24 | * Components that make up the SMRAM: |
| 25 | * 1. Save state - the total save state memory used |
| 26 | * 2. Stack - stacks for the CPUs in the SMM handler |
| 27 | * 3. Stub - SMM stub code for calling into handler |
| 28 | * 4. Handler - C-based SMM handler. |
| 29 | * |
| 30 | * The components are assumed to consist of one consecutive region. |
| 31 | */ |
| 32 | |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 33 | /* |
| 34 | * The stub is the entry point that sets up protected mode and stacks for each |
| 35 | * CPU. It then calls into the SMM handler module. It is encoded as an rmodule. |
| 36 | */ |
| 37 | extern unsigned char _binary_smmstub_start[]; |
| 38 | |
| 39 | /* Per CPU minimum stack size. */ |
| 40 | #define SMM_MINIMUM_STACK_SIZE 32 |
| 41 | |
| 42 | struct cpu_smm_info { |
| 43 | uint8_t active; |
| 44 | uintptr_t smbase; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 45 | uintptr_t ss_start; |
Arthur Heymans | cb361da | 2022-04-07 21:20:50 +0200 | [diff] [blame] | 46 | uintptr_t ss_top; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 47 | uintptr_t code_start; |
| 48 | uintptr_t code_end; |
| 49 | }; |
| 50 | struct cpu_smm_info cpus[CONFIG_MAX_CPUS] = { 0 }; |
| 51 | |
| 52 | /* |
| 53 | * This method creates a map of all the CPU entry points, save state locations |
| 54 | * and the beginning and end of code segments for each CPU. This map is used |
| 55 | * during relocation to properly align as many CPUs that can fit into the SMRAM |
| 56 | * region. For more information on how SMRAM works, refer to the latest Intel |
| 57 | * developer's manuals (volume 3, chapter 34). SMRAM is divided up into the |
| 58 | * following regions: |
| 59 | * +-----------------+ Top of SMRAM |
| 60 | * | | <- MSEG, FXSAVE |
| 61 | * +-----------------+ |
| 62 | * | common | |
| 63 | * | smi handler | 64K |
| 64 | * | | |
| 65 | * +-----------------+ |
| 66 | * | CPU 0 code seg | |
| 67 | * +-----------------+ |
| 68 | * | CPU 1 code seg | |
| 69 | * +-----------------+ |
| 70 | * | CPU x code seg | |
| 71 | * +-----------------+ |
| 72 | * | | |
| 73 | * | | |
| 74 | * +-----------------+ |
| 75 | * | stacks | |
| 76 | * +-----------------+ <- START of SMRAM |
| 77 | * |
| 78 | * The code below checks when a code segment is full and begins placing the remainder |
| 79 | * CPUs in the lower segments. The entry point for each CPU is smbase + 0x8000 |
| 80 | * and save state is smbase + 0x8000 + (0x8000 - state save size). Save state |
| 81 | * area grows downward into the CPUs entry point. Therefore staggering too many |
| 82 | * CPUs in one 32K block will corrupt CPU0's entry code as the save states move |
| 83 | * downward. |
| 84 | * input : smbase of first CPU (all other CPUs |
| 85 | * will go below this address) |
| 86 | * input : num_cpus in the system. The map will |
| 87 | * be created from 0 to num_cpus. |
| 88 | */ |
Arthur Heymans | 0ab98d5 | 2022-04-07 19:14:48 +0200 | [diff] [blame] | 89 | static int smm_create_map(const uintptr_t smbase, const unsigned int num_cpus, |
| 90 | const struct smm_loader_params *params) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 91 | { |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 92 | struct rmodule smm_stub; |
Arthur Heymans | 0ab98d5 | 2022-04-07 19:14:48 +0200 | [diff] [blame] | 93 | |
| 94 | if (ARRAY_SIZE(cpus) < num_cpus) { |
| 95 | printk(BIOS_ERR, "%s: increase MAX_CPUS in Kconfig\n", __func__); |
| 96 | return 0; |
| 97 | } |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 98 | |
| 99 | if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { |
| 100 | printk(BIOS_ERR, "%s: unable to get SMM module size\n", __func__); |
| 101 | return 0; |
| 102 | } |
| 103 | |
Arthur Heymans | 0ab98d5 | 2022-04-07 19:14:48 +0200 | [diff] [blame] | 104 | /* |
| 105 | * How many CPUs can fit into one 64K segment? |
| 106 | * Make sure that the first stub does not overlap with the last save state of a segment. |
| 107 | */ |
| 108 | const size_t stub_size = rmodule_memory_size(&smm_stub); |
| 109 | const size_t needed_ss_size = MAX(params->real_cpu_save_state_size, stub_size); |
| 110 | const size_t cpus_per_segment = |
| 111 | (SMM_CODE_SEGMENT_SIZE - SMM_ENTRY_OFFSET - stub_size) / needed_ss_size; |
| 112 | |
| 113 | if (cpus_per_segment == 0) { |
| 114 | printk(BIOS_ERR, "%s: CPUs won't fit in segment. Broken stub or save state size\n", |
| 115 | __func__); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 116 | return 0; |
| 117 | } |
| 118 | |
Arthur Heymans | 0ab98d5 | 2022-04-07 19:14:48 +0200 | [diff] [blame] | 119 | for (unsigned int i = 0; i < num_cpus; i++) { |
| 120 | if (i % cpus_per_segment == 0) |
| 121 | printk(BIOS_DEBUG, "-------------NEW CODE SEGMENT --------------\n"); |
Arthur Heymans | ff69b6f | 2022-04-07 18:33:50 +0200 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "CPU 0x%x\n", i); |
Arthur Heymans | 0ab98d5 | 2022-04-07 19:14:48 +0200 | [diff] [blame] | 123 | /* We copy the same stub for each CPU so they all need the same 'smbase'. */ |
| 124 | const size_t segment_number = i / cpus_per_segment; |
| 125 | cpus[i].smbase = smbase - SMM_CODE_SEGMENT_SIZE * segment_number |
| 126 | - needed_ss_size * (i % cpus_per_segment); |
Arthur Heymans | 1b970bd | 2022-04-07 21:16:12 +0200 | [diff] [blame] | 127 | cpus[i].code_start = cpus[i].smbase + SMM_ENTRY_OFFSET; |
| 128 | cpus[i].code_end = cpus[i].code_start + stub_size; |
Arthur Heymans | cb361da | 2022-04-07 21:20:50 +0200 | [diff] [blame] | 129 | cpus[i].ss_top = cpus[i].smbase + SMM_CODE_SEGMENT_SIZE; |
| 130 | cpus[i].ss_start = cpus[i].ss_top - params->real_cpu_save_state_size; |
Arthur Heymans | 0ab98d5 | 2022-04-07 19:14:48 +0200 | [diff] [blame] | 131 | printk(BIOS_DEBUG, " Stub [0x%lx-0x%lx[\n", cpus[i].code_start, |
Arthur Heymans | ff69b6f | 2022-04-07 18:33:50 +0200 | [diff] [blame] | 132 | cpus[i].code_end); |
Arthur Heymans | cb361da | 2022-04-07 21:20:50 +0200 | [diff] [blame] | 133 | printk(BIOS_DEBUG, " Save state [0x%lx-0x%lx[\n", cpus[i].ss_start, |
| 134 | cpus[i].ss_top); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 135 | cpus[i].active = 1; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 136 | } |
| 137 | |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 138 | return 1; |
| 139 | } |
| 140 | |
| 141 | /* |
| 142 | * This method expects the smm relocation map to be complete. |
| 143 | * This method does not read any HW registers, it simply uses a |
| 144 | * map that was created during SMM setup. |
| 145 | * input: cpu_num - cpu number which is used as an index into the |
| 146 | * map to return the smbase |
| 147 | */ |
| 148 | u32 smm_get_cpu_smbase(unsigned int cpu_num) |
| 149 | { |
| 150 | if (cpu_num < CONFIG_MAX_CPUS) { |
| 151 | if (cpus[cpu_num].active) |
| 152 | return cpus[cpu_num].smbase; |
| 153 | } |
| 154 | return 0; |
| 155 | } |
| 156 | |
| 157 | /* |
| 158 | * This method assumes that at least 1 CPU has been set up from |
| 159 | * which it will place other CPUs below its smbase ensuring that |
| 160 | * save state does not clobber the first CPUs init code segment. The init |
| 161 | * code which is the smm stub code is the same for all CPUs. They enter |
| 162 | * smm, setup stacks (based on their apic id), enter protected mode |
| 163 | * and then jump to the common smi handler. The stack is allocated |
| 164 | * at the beginning of smram (aka tseg base, not smbase). The stack |
| 165 | * pointer for each CPU is calculated by using its apic id |
| 166 | * (code is in smm_stub.s) |
| 167 | * Each entry point will now have the same stub code which, sets up the CPU |
| 168 | * stack, enters protected mode and then jumps to the smi handler. It is |
| 169 | * important to enter protected mode before the jump because the "jump to |
| 170 | * address" might be larger than the 20bit address supported by real mode. |
| 171 | * SMI entry right now is in real mode. |
| 172 | * input: smbase - this is the smbase of the first cpu not the smbase |
| 173 | * where tseg starts (aka smram_start). All CPUs code segment |
| 174 | * and stack will be below this point except for the common |
| 175 | * SMI handler which is one segment above |
| 176 | * input: num_cpus - number of cpus that need relocation including |
| 177 | * the first CPU (though its code is already loaded) |
| 178 | * input: top of stack (stacks work downward by default in Intel HW) |
| 179 | * output: return -1, if runtime smi code could not be installed. In |
| 180 | * this case SMM will not work and any SMI's generated will |
| 181 | * cause a CPU shutdown or general protection fault because |
| 182 | * the appropriate smi handling code was not installed |
| 183 | */ |
| 184 | |
| 185 | static int smm_place_entry_code(uintptr_t smbase, unsigned int num_cpus, |
Arthur Heymans | 9ddd900 | 2020-12-03 11:02:42 +0100 | [diff] [blame] | 186 | uintptr_t stack_top, const struct smm_loader_params *params) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 187 | { |
| 188 | unsigned int i; |
| 189 | unsigned int size; |
Arthur Heymans | dfff5c2 | 2021-02-15 23:39:01 +0100 | [diff] [blame] | 190 | |
| 191 | /* |
| 192 | * Ensure there was enough space and the last CPUs smbase |
| 193 | * did not encroach upon the stack. Stack top is smram start |
| 194 | * + size of stack. |
| 195 | */ |
| 196 | if (cpus[num_cpus].active) { |
Arthur Heymans | ad0116c | 2021-02-15 23:46:06 +0100 | [diff] [blame] | 197 | if (cpus[num_cpus - 1].smbase + SMM_ENTRY_OFFSET < stack_top) { |
Arthur Heymans | dfff5c2 | 2021-02-15 23:39:01 +0100 | [diff] [blame] | 198 | printk(BIOS_ERR, "%s: stack encroachment\n", __func__); |
Paul Menzel | 2ea9595 | 2021-05-16 19:53:43 +0200 | [diff] [blame] | 199 | printk(BIOS_ERR, "%s: smbase %lx, stack_top %lx\n", |
Arthur Heymans | dfff5c2 | 2021-02-15 23:39:01 +0100 | [diff] [blame] | 200 | __func__, cpus[num_cpus].smbase, stack_top); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 201 | return 0; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 202 | } |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 203 | } |
| 204 | |
Paul Menzel | 2ea9595 | 2021-05-16 19:53:43 +0200 | [diff] [blame] | 205 | printk(BIOS_INFO, "%s: smbase %lx, stack_top %lx\n", |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 206 | __func__, cpus[num_cpus-1].smbase, stack_top); |
| 207 | |
| 208 | /* start at 1, the first CPU stub code is already there */ |
| 209 | size = cpus[0].code_end - cpus[0].code_start; |
| 210 | for (i = 1; i < num_cpus; i++) { |
| 211 | memcpy((int *)cpus[i].code_start, (int *)cpus[0].code_start, size); |
| 212 | printk(BIOS_DEBUG, |
Paul Menzel | 2ea9595 | 2021-05-16 19:53:43 +0200 | [diff] [blame] | 213 | "SMM Module: placing smm entry code at %lx, cpu # 0x%x\n", |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 214 | cpus[i].code_start, i); |
Paul Menzel | 2ea9595 | 2021-05-16 19:53:43 +0200 | [diff] [blame] | 215 | printk(BIOS_DEBUG, "%s: copying from %lx to %lx 0x%x bytes\n", |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 216 | __func__, cpus[0].code_start, cpus[i].code_start, size); |
| 217 | } |
| 218 | return 1; |
| 219 | } |
| 220 | |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 221 | static uintptr_t stack_top; |
| 222 | static size_t g_stack_size; |
| 223 | |
| 224 | int smm_setup_stack(const uintptr_t perm_smbase, const size_t perm_smram_size, |
| 225 | const unsigned int total_cpus, const size_t stack_size) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 226 | { |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 227 | /* Need a minimum stack size and alignment. */ |
| 228 | if (stack_size <= SMM_MINIMUM_STACK_SIZE || (stack_size & 3) != 0) { |
| 229 | printk(BIOS_ERR, "%s: need minimum stack size\n", __func__); |
| 230 | return -1; |
| 231 | } |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 232 | |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 233 | const size_t total_stack_size = total_cpus * stack_size; |
| 234 | if (total_stack_size >= perm_smram_size) { |
| 235 | printk(BIOS_ERR, "%s: Stack won't fit smram\n", __func__); |
| 236 | return -1; |
| 237 | } |
| 238 | stack_top = perm_smbase + total_stack_size; |
| 239 | g_stack_size = stack_size; |
| 240 | return 0; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 241 | } |
| 242 | |
| 243 | /* |
| 244 | * Place the staggered entry points for each CPU. The entry points are |
| 245 | * staggered by the per CPU SMM save state size extending down from |
| 246 | * SMM_ENTRY_OFFSET. |
| 247 | */ |
| 248 | static int smm_stub_place_staggered_entry_points(char *base, |
| 249 | const struct smm_loader_params *params, const struct rmodule *smm_stub) |
| 250 | { |
| 251 | size_t stub_entry_offset; |
| 252 | int rc = 1; |
| 253 | stub_entry_offset = rmodule_entry_offset(smm_stub); |
| 254 | /* Each CPU now has its own stub code, which enters protected mode, |
| 255 | * sets up the stack, and then jumps to common SMI handler |
| 256 | */ |
| 257 | if (params->num_concurrent_save_states > 1 || stub_entry_offset != 0) { |
Arthur Heymans | 9ddd900 | 2020-12-03 11:02:42 +0100 | [diff] [blame] | 258 | rc = smm_place_entry_code((uintptr_t)base, |
| 259 | params->num_concurrent_save_states, |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 260 | stack_top, params); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 261 | } |
| 262 | return rc; |
| 263 | } |
| 264 | |
| 265 | /* |
| 266 | * The stub setup code assumes it is completely contained within the |
| 267 | * default SMRAM size (0x10000) for the default SMI handler (entry at |
| 268 | * 0x30000), but no assumption should be made for the permanent SMI handler. |
| 269 | * The placement of CPU entry points for permanent handler are determined |
| 270 | * by the number of CPUs in the system and the amount of SMRAM. |
Arthur Heymans | e6c3523 | 2021-02-16 13:19:18 +0100 | [diff] [blame] | 271 | * There are potentially 2 regions to place |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 272 | * within the default SMRAM size: |
| 273 | * 1. Save state areas |
| 274 | * 2. Stub code |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 275 | * |
Arthur Heymans | e6c3523 | 2021-02-16 13:19:18 +0100 | [diff] [blame] | 276 | * The save state always lives at the top of the CPUS smbase (and the entry |
| 277 | * point is at offset 0x8000). This allows only a certain number of CPUs with |
| 278 | * staggered entry points until the save state area comes down far enough to |
| 279 | * overwrite/corrupt the entry code (stub code). Therefore, an SMM map is |
| 280 | * created to avoid this corruption, see smm_create_map() above. |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 281 | * This module setup code works for the default (0x30000) SMM handler setup and the |
| 282 | * permanent SMM handler. |
Arthur Heymans | e6c3523 | 2021-02-16 13:19:18 +0100 | [diff] [blame] | 283 | * The CPU stack is decided at runtime in the stub and is treaded as a continuous |
| 284 | * region. As this might not fit the default SMRAM region, the same region used |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 285 | * by the permanent handler can be used during relocation. |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 286 | */ |
Arthur Heymans | cfd3224 | 2021-10-28 13:59:54 +0200 | [diff] [blame] | 287 | static int smm_module_setup_stub(const uintptr_t smbase, const size_t smm_size, |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 288 | struct smm_loader_params *params, |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 289 | void *const fxsave_area) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 290 | { |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 291 | struct rmodule smm_stub; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 292 | if (rmodule_parse(&_binary_smmstub_start, &smm_stub)) { |
| 293 | printk(BIOS_ERR, "%s: unable to parse smm stub\n", __func__); |
| 294 | return -1; |
| 295 | } |
Arthur Heymans | d7c3716 | 2022-04-07 21:41:26 +0200 | [diff] [blame^] | 296 | const size_t stub_size = rmodule_memory_size(&smm_stub); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 297 | |
Arthur Heymans | d7c3716 | 2022-04-07 21:41:26 +0200 | [diff] [blame^] | 298 | /* Some sanity check */ |
| 299 | if (stub_size >= SMM_ENTRY_OFFSET) { |
| 300 | printk(BIOS_ERR, "%s: Stub too large\n", __func__); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 301 | return -1; |
| 302 | } |
| 303 | |
Arthur Heymans | d7c3716 | 2022-04-07 21:41:26 +0200 | [diff] [blame^] | 304 | const uintptr_t smm_stub_loc = smbase + SMM_ENTRY_OFFSET; |
Arthur Heymans | cfd3224 | 2021-10-28 13:59:54 +0200 | [diff] [blame] | 305 | if (rmodule_load((void *)smm_stub_loc, &smm_stub)) { |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 306 | printk(BIOS_ERR, "%s: load module failed\n", __func__); |
| 307 | return -1; |
| 308 | } |
| 309 | |
Arthur Heymans | d7c3716 | 2022-04-07 21:41:26 +0200 | [diff] [blame^] | 310 | struct smm_stub_params *stub_params = rmodule_parameters(&smm_stub); |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 311 | stub_params->stack_top = stack_top; |
| 312 | stub_params->stack_size = g_stack_size; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 313 | stub_params->c_handler = (uintptr_t)params->handler; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 314 | stub_params->fxsave_area = (uintptr_t)fxsave_area; |
| 315 | stub_params->fxsave_area_size = FXSAVE_SIZE; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 316 | |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 317 | /* Initialize the APIC id to CPU number table to be 1:1 */ |
Arthur Heymans | d7c3716 | 2022-04-07 21:41:26 +0200 | [diff] [blame^] | 318 | for (int i = 0; i < params->num_cpus; i++) |
Arthur Heymans | ed4be45 | 2021-02-15 13:20:35 +0100 | [diff] [blame] | 319 | stub_params->apic_id_to_cpu[i] = i; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 320 | |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 321 | |
Arthur Heymans | d7c3716 | 2022-04-07 21:41:26 +0200 | [diff] [blame^] | 322 | printk(BIOS_DEBUG, "%s: stack_top = 0x%x\n", __func__, stub_params->stack_top); |
| 323 | printk(BIOS_DEBUG, "%s: per cpu stack_size = 0x%x\n", __func__, |
| 324 | stub_params->stack_size); |
| 325 | printk(BIOS_DEBUG, "%s: runtime.start32_offset = 0x%x\n", __func__, |
| 326 | stub_params->start32_offset); |
| 327 | printk(BIOS_DEBUG, "%s: runtime.smm_size = 0x%zx\n", __func__, smm_size); |
| 328 | |
| 329 | if (!smm_stub_place_staggered_entry_points((void *)smbase, params, &smm_stub)) { |
| 330 | printk(BIOS_ERR, "%s: staggered entry points failed\n", __func__); |
| 331 | return -1; |
| 332 | } |
| 333 | |
| 334 | printk(BIOS_DEBUG, "SMM Module: stub loaded at %lx. Will call %p\n", smm_stub_loc, |
| 335 | params->handler); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 336 | return 0; |
| 337 | } |
| 338 | |
| 339 | /* |
| 340 | * smm_setup_relocation_handler assumes the callback is already loaded in |
| 341 | * memory. i.e. Another SMM module isn't chained to the stub. The other |
| 342 | * assumption is that the stub will be entered from the default SMRAM |
| 343 | * location: 0x30000 -> 0x40000. |
| 344 | */ |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 345 | int smm_setup_relocation_handler(struct smm_loader_params *params) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 346 | { |
Arthur Heymans | cfd3224 | 2021-10-28 13:59:54 +0200 | [diff] [blame] | 347 | uintptr_t smram = SMM_DEFAULT_BASE; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 348 | printk(BIOS_SPEW, "%s: enter\n", __func__); |
| 349 | /* There can't be more than 1 concurrent save state for the relocation |
| 350 | * handler because all CPUs default to 0x30000 as SMBASE. */ |
| 351 | if (params->num_concurrent_save_states > 1) |
| 352 | return -1; |
| 353 | |
| 354 | /* A handler has to be defined to call for relocation. */ |
| 355 | if (params->handler == NULL) |
| 356 | return -1; |
| 357 | |
| 358 | /* Since the relocation handler always uses stack, adjust the number |
| 359 | * of concurrent stack users to be CONFIG_MAX_CPUS. */ |
Arthur Heymans | 2412c81 | 2021-10-28 15:19:39 +0200 | [diff] [blame] | 360 | if (params->num_cpus == 0) |
| 361 | params->num_cpus = CONFIG_MAX_CPUS; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 362 | |
John Zhao | 457c661 | 2021-04-21 10:13:17 -0700 | [diff] [blame] | 363 | printk(BIOS_SPEW, "%s: exit\n", __func__); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 364 | return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, |
Arthur Heymans | 96451a7 | 2021-10-28 15:14:18 +0200 | [diff] [blame] | 365 | params, fxsave_area_relocation); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 366 | } |
| 367 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 368 | static void setup_smihandler_params(struct smm_runtime *mod_params, |
| 369 | uintptr_t smram_base, |
| 370 | uintptr_t smram_size, |
| 371 | struct smm_loader_params *loader_params) |
| 372 | { |
| 373 | mod_params->smbase = smram_base; |
| 374 | mod_params->smm_size = smram_size; |
| 375 | mod_params->save_state_size = loader_params->real_cpu_save_state_size; |
| 376 | mod_params->num_cpus = loader_params->num_cpus; |
| 377 | mod_params->gnvs_ptr = (uint32_t)(uintptr_t)acpi_get_gnvs(); |
| 378 | const struct cbmem_entry *cbmemc; |
| 379 | if (CONFIG(CONSOLE_CBMEM) && (cbmemc = cbmem_entry_find(CBMEM_ID_CONSOLE))) { |
| 380 | mod_params->cbmemc = cbmem_entry_start(cbmemc); |
| 381 | mod_params->cbmemc_size = cbmem_entry_size(cbmemc); |
| 382 | } else { |
| 383 | mod_params->cbmemc = 0; |
| 384 | mod_params->cbmemc_size = 0; |
| 385 | } |
| 386 | |
Arthur Heymans | cb361da | 2022-04-07 21:20:50 +0200 | [diff] [blame] | 387 | for (int i = 0; i < loader_params->num_cpus; i++) |
| 388 | mod_params->save_state_top[i] = cpus[i].ss_top; |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 389 | } |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 390 | |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 391 | /* |
| 392 | *The SMM module is placed within the provided region in the following |
| 393 | * manner: |
| 394 | * +-----------------+ <- smram + size |
| 395 | * | BIOS resource | |
| 396 | * | list (STM) | |
| 397 | * +-----------------+ |
| 398 | * | fxsave area | |
| 399 | * +-----------------+ |
| 400 | * | smi handler | |
| 401 | * | ... | |
| 402 | * +-----------------+ <- cpu0 |
| 403 | * | stub code | <- cpu1 |
| 404 | * | stub code | <- cpu2 |
| 405 | * | stub code | <- cpu3, etc |
| 406 | * | | |
| 407 | * | | |
| 408 | * | | |
| 409 | * | stacks | |
| 410 | * +-----------------+ <- smram start |
| 411 | |
| 412 | * It should be noted that this algorithm will not work for |
| 413 | * SMM_DEFAULT_SIZE SMRAM regions such as the A segment. This algorithm |
| 414 | * expects a region large enough to encompass the handler and stacks |
| 415 | * as well as the SMM_DEFAULT_SIZE. |
| 416 | */ |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 417 | static int smm_load_module_tseg(const uintptr_t smram_base, const size_t smram_size, |
| 418 | struct smm_loader_params *params) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 419 | { |
Arthur Heymans | cfd3224 | 2021-10-28 13:59:54 +0200 | [diff] [blame] | 420 | if (smram_size <= SMM_DEFAULT_SIZE) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 421 | return -1; |
| 422 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 423 | struct rmodule smi_handler; |
| 424 | if (rmodule_parse(&_binary_smm_start, &smi_handler)) |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 425 | return -1; |
| 426 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 427 | const uintptr_t smram_top = smram_base + smram_size; |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 428 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 429 | const size_t stm_size = |
| 430 | CONFIG(STM) ? CONFIG_MSEG_SIZE - CONFIG_BIOS_RESOURCE_LIST_SIZE : 0; |
| 431 | const uintptr_t stm_base = CONFIG(STM) ? smram_top - stm_size : 0; |
| 432 | if (stm_size) { |
| 433 | printk(BIOS_DEBUG, "STM [0x%lx-0x%lx[\n", stm_base, |
| 434 | stm_base + stm_size); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 435 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 436 | printk(BIOS_DEBUG, "MSEG size 0x%x\n", CONFIG_MSEG_SIZE); |
| 437 | printk(BIOS_DEBUG, "BIOS res list 0x%x\n", CONFIG_BIOS_RESOURCE_LIST_SIZE); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 438 | } |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 439 | const size_t fx_save_area_size = CONFIG(SSE) ? FXSAVE_SIZE * params->num_cpus : 0; |
| 440 | const uintptr_t fx_save_area_base = |
| 441 | CONFIG(SSE) ? smram_top - stm_size - fx_save_area_size : 0; |
| 442 | if (fx_save_area_size) |
| 443 | printk(BIOS_DEBUG, "fx_save [0x%lx-0x%lx[\n", fx_save_area_base, |
| 444 | fx_save_area_base + fx_save_area_size); |
| 445 | const size_t handler_size = rmodule_memory_size(&smi_handler); |
| 446 | const size_t handler_alignment = rmodule_load_alignment(&smi_handler); |
| 447 | const uintptr_t handler_base = |
| 448 | ALIGN_DOWN(smram_top - stm_size - fx_save_area_size - handler_size, |
| 449 | handler_alignment); |
| 450 | printk(BIOS_DEBUG, "smihandler [0x%lx-0x%lx[\n", handler_base, |
| 451 | handler_base + handler_size); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 452 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 453 | if (handler_base <= smram_base) { |
| 454 | printk(BIOS_ERR, "Permanent handler won't FIT smram\n"); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 455 | return -1; |
| 456 | } |
| 457 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 458 | const uintptr_t stub_segment_base = handler_base - SMM_CODE_SEGMENT_SIZE; |
| 459 | if (!smm_create_map(stub_segment_base, params->num_concurrent_save_states, params)) { |
Arthur Heymans | dfff5c2 | 2021-02-15 23:39:01 +0100 | [diff] [blame] | 460 | printk(BIOS_ERR, "%s: Error creating CPU map\n", __func__); |
| 461 | return -1; |
| 462 | } |
| 463 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 464 | const uintptr_t lowest_stub = cpus[params->num_concurrent_save_states - 1].code_start; |
| 465 | const uintptr_t smm_stack_top = |
| 466 | smram_base + params->num_concurrent_save_states * CONFIG_SMM_MODULE_STACK_SIZE; |
| 467 | printk(BIOS_DEBUG, "cpu stacks [0x%lx-0x%lx[\n", smram_base, smm_stack_top); |
| 468 | if (lowest_stub < smm_stack_top) { |
| 469 | printk(BIOS_ERR, "SMM stubs won't fit in SMRAM 0x%lx\n", |
| 470 | cpus[params->num_concurrent_save_states - 1].code_start); |
| 471 | return -1; |
Arthur Heymans | 64d9e85 | 2021-02-15 18:55:40 +0100 | [diff] [blame] | 472 | } |
| 473 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 474 | if (rmodule_load((void *)handler_base, &smi_handler)) |
| 475 | return -1; |
| 476 | |
| 477 | struct smm_runtime *smihandler_params = rmodule_parameters(&smi_handler); |
| 478 | params->handler = rmodule_entry(&smi_handler); |
| 479 | setup_smihandler_params(smihandler_params, smram_base, smram_size, params); |
| 480 | |
| 481 | return smm_module_setup_stub(stub_segment_base, smram_size, params, |
| 482 | (void *)fx_save_area_base); |
Rocky Phagura | afb7a81 | 2020-07-21 14:48:48 -0700 | [diff] [blame] | 483 | } |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 484 | |
| 485 | /* |
| 486 | *The SMM module is placed within the provided region in the following |
| 487 | * manner: |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 488 | * +-----------------+ <- smram + size == 0xB0000 |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 489 | * | save states | |
| 490 | * +-----------------+ |
| 491 | * | fxsave area | |
| 492 | * +-----------------+ |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 493 | * | smi handler | (or below the stubs if there is more space there) |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 494 | * | ... | |
| 495 | * +-----------------+ <- cpu0 |
| 496 | * | stub code | <- cpu1 |
| 497 | * | stub code | <- cpu2 |
| 498 | * | stub code | <- cpu3, etc |
| 499 | * | | |
| 500 | * | | |
| 501 | * | | |
| 502 | * | stacks | |
| 503 | * +-----------------+ <- smram start = 0xA0000 |
| 504 | */ |
| 505 | static int smm_load_module_aseg(const uintptr_t smram_base, const size_t smram_size, |
| 506 | struct smm_loader_params *params) |
| 507 | { |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 508 | if (smram_size != SMM_DEFAULT_SIZE) |
| 509 | return -1; |
| 510 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 511 | struct rmodule smi_handler; |
| 512 | if (rmodule_parse(&_binary_smm_start, &smi_handler)) |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 513 | return -1; |
| 514 | |
| 515 | if (!smm_create_map(smram_base, params->num_concurrent_save_states, params)) { |
| 516 | printk(BIOS_ERR, "%s: Error creating CPU map\n", __func__); |
| 517 | return -1; |
| 518 | } |
| 519 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 520 | const uintptr_t smm_stack_top = |
| 521 | smram_base + params->num_concurrent_save_states * CONFIG_SMM_MODULE_STACK_SIZE; |
| 522 | printk(BIOS_DEBUG, "cpu stacks [0x%lx-0x%lx[\n", smram_base, smm_stack_top); |
| 523 | if (smm_stack_top > cpus[params->num_concurrent_save_states - 1].code_start) { |
| 524 | printk(BIOS_ERR, "stack won't fit in smram\n"); |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 525 | return -1; |
| 526 | } |
| 527 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 528 | const uintptr_t save_state_bottom = |
| 529 | cpus[params->num_concurrent_save_states - 1].ss_start; |
| 530 | const size_t fx_save_area_size = CONFIG(SSE) ? FXSAVE_SIZE * params->num_cpus : 0; |
| 531 | const uintptr_t fx_save_area_base = |
| 532 | CONFIG(SSE) ? save_state_bottom - fx_save_area_size : 0; |
| 533 | if (fx_save_area_size) { |
| 534 | printk(BIOS_DEBUG, "fx_save [0x%lx-0x%lx[\n", fx_save_area_base, |
| 535 | fx_save_area_base + fx_save_area_size); |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 536 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 537 | if (fx_save_area_base < cpus[0].code_end) { |
| 538 | printk(BIOS_ERR, "fxsave won't fit in smram\n"); |
| 539 | return -1; |
| 540 | } |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 541 | } |
| 542 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 543 | const size_t top_space = save_state_bottom - fx_save_area_size - cpus[0].code_end; |
| 544 | const size_t bottom_space = |
| 545 | cpus[params->num_concurrent_save_states - 1].code_start - smm_stack_top; |
| 546 | const bool use_top = top_space >= bottom_space; |
| 547 | |
| 548 | const size_t handler_size = rmodule_memory_size(&smi_handler); |
| 549 | const size_t handler_alignment = rmodule_load_alignment(&smi_handler); |
| 550 | uintptr_t handler_base; |
| 551 | if (use_top) { |
| 552 | handler_base = ALIGN_DOWN(save_state_bottom - fx_save_area_size - handler_size, |
| 553 | handler_alignment); |
| 554 | if (handler_base < cpus[0].code_end) { |
| 555 | printk(BIOS_ERR, "handler won't fit in top of smram\n"); |
| 556 | return -1; |
| 557 | } |
| 558 | } else { |
| 559 | handler_base = ALIGN_UP(stack_top, handler_alignment); |
| 560 | const uintptr_t handler_top = handler_base + handler_size; |
| 561 | if (handler_top > cpus[params->num_concurrent_save_states - 1].code_start) { |
| 562 | printk(BIOS_ERR, "handler won't fit in bottom of smram\n"); |
| 563 | return -1; |
| 564 | } |
| 565 | } |
| 566 | printk(BIOS_DEBUG, "handler [0x%lx-0x%lx[\n", handler_base, |
| 567 | handler_base + handler_size); |
| 568 | |
| 569 | if (rmodule_load((void *)handler_base, &smi_handler)) |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 570 | return -1; |
| 571 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 572 | struct smm_runtime *smihandler_params = rmodule_parameters(&smi_handler); |
| 573 | params->handler = rmodule_entry(&smi_handler); |
| 574 | setup_smihandler_params(smihandler_params, smram_base, smram_size, params); |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 575 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 576 | return smm_module_setup_stub(smram_base, smram_size, params, |
| 577 | (void *)fx_save_area_base); |
| 578 | } |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 579 | |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 580 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 581 | int smm_load_module(const uintptr_t smram_base, const size_t smram_size, |
| 582 | struct smm_loader_params *params) |
| 583 | { |
| 584 | if (CONFIG(SMM_ASEG)) |
| 585 | return smm_load_module_aseg(smram_base, smram_size, params); |
| 586 | else if (CONFIG(SMM_TSEG)) |
| 587 | return smm_load_module_tseg(smram_base, smram_size, params); |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 588 | |
Arthur Heymans | 5747f6c | 2022-04-07 20:54:26 +0200 | [diff] [blame] | 589 | return -1; |
Arthur Heymans | b4ba289 | 2021-10-28 16:48:36 +0200 | [diff] [blame] | 590 | } |