Angel Pons | 0612b27 | 2020-04-05 15:46:56 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 2 | |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 3 | #include <assert.h> |
| 4 | #include <bootstate.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 6 | #include <cpu/cpu.h> |
| 7 | #include <cpu/x86/mtrr.h> |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 8 | #include <cpu/x86/mp.h> |
| 9 | #include <cpu/intel/microcode.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 10 | #include <intelblocks/cfg.h> |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 11 | #include <intelblocks/cpulib.h> |
| 12 | #include <intelblocks/fast_spi.h> |
| 13 | #include <intelblocks/mp_init.h> |
| 14 | #include <intelblocks/msr.h> |
| 15 | #include <soc/cpu.h> |
| 16 | |
Subrata Banik | bdea352 | 2022-05-31 23:36:59 +0530 | [diff] [blame] | 17 | static void initialize_microcode(void) |
| 18 | { |
| 19 | const void *microcode_patch = intel_microcode_find(); |
| 20 | intel_microcode_load_unlocked(microcode_patch); |
| 21 | } |
| 22 | |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 23 | static void init_one_cpu(struct device *dev) |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 24 | { |
Pratik Prajapati | 9cd6a26 | 2017-08-14 13:57:46 -0700 | [diff] [blame] | 25 | soc_core_init(dev); |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 26 | |
Subrata Banik | bdea352 | 2022-05-31 23:36:59 +0530 | [diff] [blame] | 27 | initialize_microcode(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 28 | } |
| 29 | |
| 30 | static struct device_operations cpu_dev_ops = { |
| 31 | .init = init_one_cpu, |
| 32 | }; |
| 33 | |
Jonathan Neuschäfer | 8f06ce3 | 2017-11-20 01:56:44 +0100 | [diff] [blame] | 34 | static const struct cpu_device_id cpu_table[] = { |
Felix Held | 6a6ac1e | 2023-02-06 15:19:11 +0100 | [diff] [blame] | 35 | { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1, CPUID_EXACT_MATCH_MASK }, |
| 36 | { X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2, CPUID_EXACT_MATCH_MASK }, |
Musse Abdullahi | ab496bf | 2023-04-10 18:07:14 -0700 | [diff] [blame] | 37 | { X86_VENDOR_INTEL, CPUID_METEORLAKE_B0, CPUID_EXACT_MATCH_MASK }, |
Musse Abdullahi | 08545aa | 2023-06-27 11:14:09 -0700 | [diff] [blame] | 38 | { X86_VENDOR_INTEL, CPUID_METEORLAKE_C0, CPUID_EXACT_MATCH_MASK }, |
Felix Held | 6a6ac1e | 2023-02-06 15:19:11 +0100 | [diff] [blame] | 39 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0, CPUID_EXACT_MATCH_MASK }, |
| 40 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0, CPUID_EXACT_MATCH_MASK }, |
| 41 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0, CPUID_EXACT_MATCH_MASK }, |
| 42 | { X86_VENDOR_INTEL, CPUID_SKYLAKE_HR0, CPUID_EXACT_MATCH_MASK }, |
| 43 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_G0, CPUID_EXACT_MATCH_MASK }, |
| 44 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_H0, CPUID_EXACT_MATCH_MASK }, |
| 45 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_Y0, CPUID_EXACT_MATCH_MASK }, |
| 46 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_HA0, CPUID_EXACT_MATCH_MASK }, |
| 47 | { X86_VENDOR_INTEL, CPUID_KABYLAKE_HB0, CPUID_EXACT_MATCH_MASK }, |
| 48 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_A0, CPUID_EXACT_MATCH_MASK }, |
| 49 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_B0, CPUID_EXACT_MATCH_MASK }, |
| 50 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_C0, CPUID_EXACT_MATCH_MASK }, |
| 51 | { X86_VENDOR_INTEL, CPUID_CANNONLAKE_D0, CPUID_EXACT_MATCH_MASK }, |
| 52 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0, CPUID_EXACT_MATCH_MASK }, |
| 53 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_B0, CPUID_EXACT_MATCH_MASK }, |
| 54 | { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_E0, CPUID_EXACT_MATCH_MASK }, |
| 55 | { X86_VENDOR_INTEL, CPUID_GLK_A0, CPUID_EXACT_MATCH_MASK }, |
| 56 | { X86_VENDOR_INTEL, CPUID_GLK_B0, CPUID_EXACT_MATCH_MASK }, |
| 57 | { X86_VENDOR_INTEL, CPUID_GLK_R0, CPUID_EXACT_MATCH_MASK }, |
| 58 | { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_V0, CPUID_EXACT_MATCH_MASK }, |
| 59 | { X86_VENDOR_INTEL, CPUID_WHISKEYLAKE_W0, CPUID_EXACT_MATCH_MASK }, |
| 60 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_U0, CPUID_EXACT_MATCH_MASK }, |
| 61 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_B0, CPUID_EXACT_MATCH_MASK }, |
| 62 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_P0, CPUID_EXACT_MATCH_MASK }, |
| 63 | { X86_VENDOR_INTEL, CPUID_COFFEELAKE_R0, CPUID_EXACT_MATCH_MASK }, |
| 64 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_A0, CPUID_EXACT_MATCH_MASK }, |
| 65 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_U_K0_S0, CPUID_EXACT_MATCH_MASK }, |
| 66 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G0, CPUID_EXACT_MATCH_MASK }, |
| 67 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_6_2_G1, CPUID_EXACT_MATCH_MASK }, |
| 68 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P0, CPUID_EXACT_MATCH_MASK }, |
| 69 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_P1, CPUID_EXACT_MATCH_MASK }, |
| 70 | { X86_VENDOR_INTEL, CPUID_COMETLAKE_H_S_10_2_Q0, CPUID_EXACT_MATCH_MASK }, |
| 71 | { X86_VENDOR_INTEL, CPUID_TIGERLAKE_A0, CPUID_EXACT_MATCH_MASK }, |
| 72 | { X86_VENDOR_INTEL, CPUID_TIGERLAKE_B0, CPUID_EXACT_MATCH_MASK }, |
| 73 | { X86_VENDOR_INTEL, CPUID_TIGERLAKE_R0, CPUID_EXACT_MATCH_MASK }, |
| 74 | { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0, CPUID_EXACT_MATCH_MASK }, |
| 75 | { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0, CPUID_EXACT_MATCH_MASK }, |
| 76 | { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0, CPUID_EXACT_MATCH_MASK }, |
Michał Żygowski | d54a5b29 | 2023-07-03 17:17:32 +0200 | [diff] [blame^] | 77 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0, CPUID_EXACT_MATCH_MASK }, |
Felix Held | 6a6ac1e | 2023-02-06 15:19:11 +0100 | [diff] [blame] | 78 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0, CPUID_EXACT_MATCH_MASK }, |
| 79 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0, CPUID_EXACT_MATCH_MASK }, |
| 80 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0, CPUID_EXACT_MATCH_MASK }, |
| 81 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0, CPUID_EXACT_MATCH_MASK }, |
| 82 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0, CPUID_EXACT_MATCH_MASK }, |
| 83 | { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0, CPUID_EXACT_MATCH_MASK }, |
Michał Żygowski | d54a5b29 | 2023-07-03 17:17:32 +0200 | [diff] [blame^] | 84 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_J0, CPUID_EXACT_MATCH_MASK }, |
| 85 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_Q0, CPUID_EXACT_MATCH_MASK }, |
| 86 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_A0, CPUID_EXACT_MATCH_MASK }, |
| 87 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_B0, CPUID_EXACT_MATCH_MASK }, |
| 88 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_C0, CPUID_EXACT_MATCH_MASK }, |
| 89 | { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_H0, CPUID_EXACT_MATCH_MASK }, |
Felix Held | 1e78165 | 2023-02-08 11:39:16 +0100 | [diff] [blame] | 90 | CPU_TABLE_END |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 91 | }; |
| 92 | |
| 93 | static const struct cpu_driver driver __cpu_driver = { |
| 94 | .ops = &cpu_dev_ops, |
| 95 | .id_table = cpu_table, |
| 96 | }; |
| 97 | |
| 98 | /* |
| 99 | * MP Init callback function to Find CPU Topology. This function is common |
| 100 | * among all SOCs and thus its in Common CPU block. |
| 101 | */ |
| 102 | int get_cpu_count(void) |
| 103 | { |
| 104 | unsigned int num_virt_cores, num_phys_cores; |
| 105 | |
| 106 | cpu_read_topology(&num_phys_cores, &num_virt_cores); |
| 107 | |
| 108 | printk(BIOS_DEBUG, "Detected %u core, %u thread CPU.\n", |
| 109 | num_phys_cores, num_virt_cores); |
| 110 | |
| 111 | return num_virt_cores; |
| 112 | } |
| 113 | |
| 114 | /* |
| 115 | * MP Init callback function(get_microcode_info) to find the Microcode at |
| 116 | * Pre MP Init phase. This function is common among all SOCs and thus its in |
| 117 | * Common CPU block. |
| 118 | * This function also fills in the microcode patch (in *microcode), and also |
| 119 | * sets the argument *parallel to 1, which allows microcode loading in all |
| 120 | * APs to occur in parallel during MP Init. |
| 121 | */ |
| 122 | void get_microcode_info(const void **microcode, int *parallel) |
| 123 | { |
Patrick Rudolph | 3fa23b8 | 2021-01-25 09:42:08 +0100 | [diff] [blame] | 124 | *microcode = intel_microcode_find(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 125 | *parallel = 1; |
| 126 | } |
| 127 | |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 128 | /* |
| 129 | * Perform BSP and AP initialization |
| 130 | * This function can be called in below cases: |
| 131 | * 1. During coreboot is doing MP initialization as part of BS_DEV_INIT_CHIPS (exclude |
| 132 | * this call if user has selected USE_INTEL_FSP_MP_INIT). |
| 133 | * 2. coreboot would like to take APs control back after FSP-S has done with MP |
| 134 | * initialization based on user select USE_INTEL_FSP_MP_INIT. |
MAULIK V VAGHELA | 3c0ecd5 | 2021-08-02 13:11:46 +0530 | [diff] [blame] | 135 | * |
| 136 | * This function would use cpu_cluster as a device and APIC device as a linked list to |
| 137 | * the cpu cluster. This function adds a node in case the mainboard doesn't have a lapic id |
| 138 | * hardcoded in devicetree, and then fills with the actual BSP APIC ID. |
| 139 | * This allows coreboot to dynamically detect the LAPIC ID of BSP. |
| 140 | * In case the mainboard has an APIC ID defined in devicetree, a link will be present and |
| 141 | * creation of the new node will be skipped. This node will have the APIC ID defined |
| 142 | * in devicetree. |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 143 | */ |
Arthur Heymans | 829e8e6 | 2023-01-30 19:09:34 +0100 | [diff] [blame] | 144 | static void init_cpus(void) |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 145 | { |
Elyes HAOUAS | 68c851b | 2018-06-12 22:06:09 +0200 | [diff] [blame] | 146 | struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 147 | assert(dev != NULL); |
| 148 | |
Arthur Heymans | 829e8e6 | 2023-01-30 19:09:34 +0100 | [diff] [blame] | 149 | mp_cpu_bus_init(dev); |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | static void coreboot_init_cpus(void *unused) |
| 153 | { |
Subrata Banik | cf32fd1 | 2018-12-19 18:02:17 +0530 | [diff] [blame] | 154 | if (CONFIG(USE_INTEL_FSP_MP_INIT)) |
Subrata Banik | f699c14 | 2018-06-08 17:57:37 +0530 | [diff] [blame] | 155 | return; |
| 156 | |
Subrata Banik | bdea352 | 2022-05-31 23:36:59 +0530 | [diff] [blame] | 157 | initialize_microcode(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 158 | |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 159 | init_cpus(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 160 | } |
| 161 | |
Subrata Banik | 73ad818 | 2022-03-15 18:29:33 +0530 | [diff] [blame] | 162 | static void post_cpus_add_romcache(void) |
| 163 | { |
| 164 | if (!CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) |
| 165 | return; |
| 166 | |
| 167 | fast_spi_cache_bios_region(); |
| 168 | } |
| 169 | |
Subrata Banik | 3337497 | 2018-04-24 13:45:30 +0530 | [diff] [blame] | 170 | static void wrapper_x86_setup_mtrrs(void *unused) |
| 171 | { |
| 172 | x86_setup_mtrrs_with_detect(); |
| 173 | } |
| 174 | |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 175 | static void wrapper_set_bios_done(void *unused) |
| 176 | { |
| 177 | cpu_soc_bios_done(); |
| 178 | } |
| 179 | |
Subrata Banik | 861ec01 | 2022-06-16 00:02:39 +0530 | [diff] [blame] | 180 | static void wrapper_init_core_prmrr(void *unused) |
| 181 | { |
| 182 | init_core_prmrr(); |
| 183 | } |
| 184 | |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 185 | void before_post_cpus_init(void) |
| 186 | { |
Subrata Banik | 957609d | 2022-06-16 20:25:08 +0530 | [diff] [blame] | 187 | /* |
| 188 | * Ensure all APs finish the task and continue if coreboot decides to |
| 189 | * perform multiprocessor initialization using native coreboot drivers |
| 190 | * instead using FSP MP PPI implementation. |
| 191 | * |
| 192 | * Ignore if USE_COREBOOT_MP_INIT is not enabled. |
| 193 | */ |
| 194 | if (!CONFIG(USE_COREBOOT_MP_INIT)) |
| 195 | return; |
| 196 | |
Subrata Banik | 5a9b7aa | 2022-08-12 17:14:43 +0530 | [diff] [blame] | 197 | if (mp_run_on_all_cpus(wrapper_init_core_prmrr, NULL) != CB_SUCCESS) |
Subrata Banik | 861ec01 | 2022-06-16 00:02:39 +0530 | [diff] [blame] | 198 | printk(BIOS_ERR, "core PRMRR sync failure\n"); |
| 199 | |
Subrata Banik | 5a9b7aa | 2022-08-12 17:14:43 +0530 | [diff] [blame] | 200 | if (mp_run_on_all_cpus(wrapper_set_bios_done, NULL) != CB_SUCCESS) |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 201 | printk(BIOS_ERR, "Set BIOS Done failure\n"); |
Subrata Banik | f4fe21d | 2022-05-31 23:43:36 +0530 | [diff] [blame] | 202 | |
Subrata Banik | 46265ab | 2022-06-15 21:39:06 +0530 | [diff] [blame] | 203 | intel_reload_microcode(); |
Subrata Banik | e43adb6 | 2022-05-31 23:28:57 +0530 | [diff] [blame] | 204 | } |
| 205 | |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 206 | /* Ensure to re-program all MTRRs based on DRAM resource settings */ |
| 207 | static void post_cpus_init(void *unused) |
| 208 | { |
Kane Chen | 2e96eeb | 2022-04-12 09:12:59 +0800 | [diff] [blame] | 209 | /* Ensure all APs finish the task and continue */ |
| 210 | if (mp_run_on_all_cpus_synchronously(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 211 | printk(BIOS_ERR, "MTRR programming failure\n"); |
| 212 | |
Subrata Banik | 73ad818 | 2022-03-15 18:29:33 +0530 | [diff] [blame] | 213 | post_cpus_add_romcache(); |
Barnali Sarkar | 91d38a5b | 2017-06-13 19:17:35 +0530 | [diff] [blame] | 214 | x86_mtrr_check(); |
| 215 | } |
| 216 | |
| 217 | /* Do CPU MP Init before FSP Silicon Init */ |
Subrata Banik | a3c33c6 | 2020-07-31 11:47:42 +0530 | [diff] [blame] | 218 | BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, coreboot_init_cpus, NULL); |
Barnali Sarkar | f43adf0 | 2017-12-27 13:48:58 +0530 | [diff] [blame] | 219 | BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, post_cpus_init, NULL); |
| 220 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, post_cpus_init, NULL); |