commit | 3c0ecd57c174b7391c66d22406effe18ce570cac | [log] [tgz] |
---|---|---|
author | MAULIK V VAGHELA <maulik.v.vaghela@intel.com> | Mon Aug 02 13:11:46 2021 +0530 |
committer | Subrata Banik <subrata.banik@intel.com> | Mon Aug 09 06:13:07 2021 +0000 |
tree | 2f22e85a55e9f7e20d235bb96926515816bf3984 | |
parent | 43a3aa0cf4ef427de6b2e445598c4aa300718bb1 [diff] |
soc/intel/common/cpu: Handle non-zero BSP APIC ID in init_cpus coreboot always assumes that BSP APIC ID will always be 0 but as per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, it says that BSP can be any processor whose index/APIC ID might not be 0. To handle this situation, init_cpu call is required to modify to handle dynamic detection of APIC ID from BSP instead of hardcoding always through devicetree. Function has been updated to create a new node with actual BSP APIC ID when devicetree doesn't contain APIC ID defined. In case APID ID is defined, function will use a node with the APIC ID defined in devicetree. Changes also requires to remove "lapic 0" hardcoding from devicetree to allow code to fill BSP APIC ID dynamically. Otherwise coreboot will create an extra node for CPU with APIC ID 0 and it'll show as a extra node in kernel. This will cause kernel to report wrong (extra) core count information then actually present. BUG=None BRANCH=None TEST=Boot the JSL system and observe there is no functional impacts. Without this CL kernel core count in `lscpu` = 3 With this CL, kernel core count is corrected to 2. Change-Id: Ib14a5c31b3afb0d773284c684bd1994a78b94445 Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you're feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.