Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 2 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 3 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 4 | #include <device/pci_ops.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 5 | #include <device/pci_def.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 6 | #include <northbridge/intel/pineview/pineview.h> |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 7 | #include <northbridge/intel/pineview/chip.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 8 | #include <option.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 9 | #include <types.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 10 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 11 | #define LPC_DEV PCI_DEV(0, 0x1f, 0) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 12 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 13 | #define CRCLK_PINEVIEW 0x02 |
| 14 | #define CDCLK_PINEVIEW 0x10 |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 15 | |
| 16 | static void early_graphics_setup(void) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 17 | { |
| 18 | u8 reg8; |
| 19 | u16 reg16; |
| 20 | u32 reg32; |
| 21 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 22 | const struct device *d0f0 = pcidev_on_root(0, 0); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 23 | const struct northbridge_intel_pineview_config *config = d0f0->chip_info; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 24 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 25 | pci_write_config8(HOST_BRIDGE, DEVEN, BOARD_DEVEN); |
Arthur Heymans | 2a0e998 | 2017-01-14 17:32:20 +0100 | [diff] [blame] | 26 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 27 | /* Fetch VRAM size from CMOS option */ |
Angel Pons | 88dcb31 | 2021-04-26 17:10:28 +0200 | [diff] [blame] | 28 | reg8 = get_uint_option("gfx_uma_size", 0); /* 0 for 8MB */ |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 29 | |
| 30 | /* Ensure the setting is valid */ |
Arthur Heymans | 2a0e998 | 2017-01-14 17:32:20 +0100 | [diff] [blame] | 31 | if (reg8 > 6) |
| 32 | reg8 = 0; |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 33 | |
Arthur Heymans | 2a0e998 | 2017-01-14 17:32:20 +0100 | [diff] [blame] | 34 | /* Select 1M GTT */ |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 35 | pci_write_config16(HOST_BRIDGE, GGC, (1 << 8) | ((reg8 + 3) << 4)); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 36 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 37 | printk(BIOS_SPEW, "Set GFX clocks..."); |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 38 | reg16 = mchbar_read16(MCH_GCFGC); |
| 39 | mchbar_write16(MCH_GCFGC, reg16 | 1 << 9); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 40 | reg16 &= ~0x7f; |
| 41 | reg16 |= CDCLK_PINEVIEW | CRCLK_PINEVIEW; |
| 42 | reg16 &= ~(1 << 9); |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 43 | mchbar_write16(MCH_GCFGC, reg16); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 44 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 45 | /* Graphics core */ |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 46 | reg8 = mchbar_read8(HPLLVCO); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 47 | reg8 &= 0x7; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 48 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 49 | reg16 = pci_read_config16(GMCH_IGD, 0xcc) & ~0x1ff; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 50 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 51 | if (reg8 == 0x4) { |
| 52 | /* 2666MHz */ |
| 53 | reg16 |= 0xad; |
| 54 | } else if (reg8 == 0) { |
| 55 | /* 3200MHz */ |
| 56 | reg16 |= 0xa0; |
| 57 | } else if (reg8 == 1) { |
| 58 | /* 4000MHz */ |
| 59 | reg16 |= 0xad; |
| 60 | } |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 61 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 62 | pci_write_config16(GMCH_IGD, 0xcc, reg16); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 63 | |
Angel Pons | 26766fd | 2020-06-08 12:38:19 +0200 | [diff] [blame] | 64 | pci_and_config8(GMCH_IGD, 0x62, ~0x3); |
| 65 | pci_or_config8(GMCH_IGD, 0x62, 2); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 66 | |
| 67 | if (config->use_crt) { |
| 68 | /* Enable VGA */ |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 69 | mchbar_setbits32(DACGIOCTRL1, 1 << 15); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 70 | } else { |
| 71 | /* Disable VGA */ |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 72 | mchbar_clrbits32(DACGIOCTRL1, 1 << 15); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | if (config->use_lvds) { |
| 76 | /* Enable LVDS */ |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 77 | reg32 = mchbar_read32(LVDSICR2); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 78 | reg32 &= ~0xf1000000; |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 79 | reg32 |= 0x90000000; |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 80 | mchbar_write32(LVDSICR2, reg32); |
| 81 | mchbar_setbits32(IOCKTRR1, 1 << 9); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 82 | } else { |
| 83 | /* Disable LVDS */ |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 84 | mchbar_setbits32(DACGIOCTRL1, 3 << 25); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 85 | } |
| 86 | |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 87 | mchbar_write32(CICTRL, 0xc6db8b5f); |
| 88 | mchbar_write16(CISDCTRL, 0x024f); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 89 | |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 90 | mchbar_clrbits32(DACGIOCTRL1, 0xff); |
| 91 | mchbar_setbits32(DACGIOCTRL1, 1 << 5); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 92 | |
| 93 | /* Legacy backlight control */ |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 94 | pci_write_config8(GMCH_IGD, 0xf4, 0x4c); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 95 | } |
| 96 | |
| 97 | static void early_misc_setup(void) |
| 98 | { |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 99 | mchbar_read32(HIT0); |
| 100 | mchbar_write32(HIT0, 0x00021800); |
| 101 | dmibar_write32(0x2c, 0x86000040); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 102 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); |
| 103 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 104 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 105 | early_graphics_setup(); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 106 | |
Angel Pons | 0aeaee7 | 2021-03-26 17:57:46 +0100 | [diff] [blame] | 107 | mchbar_read32(HIT4); |
| 108 | mchbar_write32(HIT4, 0); |
| 109 | mchbar_read32(HIT4); |
| 110 | mchbar_write32(HIT4, 1 << 3); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 111 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 112 | pci_write_config8(LPC_DEV, 0x08, 0x1d); |
| 113 | pci_write_config8(LPC_DEV, 0x08, 0x00); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 114 | RCBA32(0x3410) = 0x00020465; |
Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 115 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 116 | pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); |
| 117 | pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); |
| 118 | pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1); |
| 119 | pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1); |
| 120 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 121 | RCBA32(0x3100) = 0x00042210; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 122 | RCBA32(0x3108) = 0x10004321; |
| 123 | RCBA32(0x310c) = 0x00214321; |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 124 | RCBA32(0x3110) = 1; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 125 | RCBA32(0x3140) = 0x01460132; |
| 126 | RCBA32(0x3142) = 0x02370146; |
| 127 | RCBA32(0x3144) = 0x32010237; |
| 128 | RCBA32(0x3146) = 0x01463201; |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 129 | RCBA32(0x3148) = 0x00000146; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | static void pineview_setup_bars(void) |
| 133 | { |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 134 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 135 | pci_write_config8(HOST_BRIDGE, 0x08, 0x69); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 136 | |
| 137 | /* Set up all hardcoded northbridge BARs */ |
Angel Pons | 24b1d8a | 2021-01-20 12:00:31 +0100 | [diff] [blame] | 138 | pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); |
| 139 | pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); |
| 140 | pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 141 | pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 142 | |
| 143 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 144 | pci_write_config8(HOST_BRIDGE, PAM0, 0x30); |
| 145 | pci_write_config8(HOST_BRIDGE, PAM1, 0x33); |
| 146 | pci_write_config8(HOST_BRIDGE, PAM2, 0x33); |
| 147 | pci_write_config8(HOST_BRIDGE, PAM3, 0x33); |
| 148 | pci_write_config8(HOST_BRIDGE, PAM4, 0x33); |
| 149 | pci_write_config8(HOST_BRIDGE, PAM5, 0x33); |
| 150 | pci_write_config8(HOST_BRIDGE, PAM6, 0x33); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 151 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 152 | printk(BIOS_DEBUG, " done.\n"); |
| 153 | } |
| 154 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 155 | void pineview_early_init(void) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 156 | { |
| 157 | /* Print some chipset specific information */ |
| 158 | printk(BIOS_DEBUG, "Intel Pineview northbridge\n"); |
| 159 | |
| 160 | /* Setup all BARs required for early PCIe and raminit */ |
| 161 | pineview_setup_bars(); |
| 162 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 163 | /* Miscellaneous setup */ |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 164 | early_misc_setup(); |
| 165 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 166 | /* Route port80 to LPC */ |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 167 | RCBA32(GCS) &= (~0x04); |
| 168 | RCBA32(0x2010) |= (1 << 10); |
| 169 | } |