Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 17 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 19 | #include <device/pci_def.h> |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 20 | #include <device/pci.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 21 | #include <northbridge/intel/pineview/pineview.h> |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 22 | #include <northbridge/intel/pineview/chip.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame^] | 23 | #include <option.h> |
Elyes HAOUAS | 51401c3 | 2019-05-15 21:09:30 +0200 | [diff] [blame] | 24 | #include <types.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 25 | |
| 26 | #define LPC PCI_DEV(0, 0x1f, 0) |
| 27 | #define D0F0 PCI_DEV(0, 0, 0) |
| 28 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 29 | #define PCI_GCFC 0xf0 |
| 30 | #define MCH_GCFGC 0xc8c |
| 31 | #define CRCLK_PINEVIEW 0x02 |
| 32 | #define CDCLK_PINEVIEW 0x10 |
| 33 | #define MCH_HPLLVCO 0xc38 |
| 34 | |
| 35 | static void early_graphics_setup(void) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 36 | { |
| 37 | u8 reg8; |
| 38 | u16 reg16; |
| 39 | u32 reg32; |
| 40 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 41 | const struct device *d0f0 = pcidev_on_root(0, 0); |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 42 | const struct northbridge_intel_pineview_config *config = d0f0->chip_info; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 43 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 44 | pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); |
Arthur Heymans | 2a0e998 | 2017-01-14 17:32:20 +0100 | [diff] [blame] | 45 | |
| 46 | /* vram size from cmos option */ |
| 47 | if (get_option(®8, "gfx_uma_size") != CB_SUCCESS) |
| 48 | reg8 = 0; /* 0 for 8MB */ |
| 49 | /* make sure no invalid setting is used */ |
| 50 | if (reg8 > 6) |
| 51 | reg8 = 0; |
| 52 | /* Select 1M GTT */ |
| 53 | pci_write_config16(PCI_DEV(0, 0x00, 0), GGC, (1 << 8) |
| 54 | | ((reg8 + 3) << 4)); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 55 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 56 | printk(BIOS_SPEW, "Set GFX clocks..."); |
| 57 | reg16 = MCHBAR16(MCH_GCFGC); |
| 58 | MCHBAR16(MCH_GCFGC) = reg16 | (1 << 9); |
| 59 | reg16 &= ~0x7f; |
| 60 | reg16 |= CDCLK_PINEVIEW | CRCLK_PINEVIEW; |
| 61 | reg16 &= ~(1 << 9); |
| 62 | MCHBAR16(MCH_GCFGC) = reg16; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 63 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 64 | /* Graphics core */ |
| 65 | reg8 = MCHBAR8(MCH_HPLLVCO); |
| 66 | reg8 &= 0x7; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 67 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 68 | reg16 = pci_read_config16(PCI_DEV(0,2,0), 0xcc) & ~0x1ff; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 69 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 70 | if (reg8 == 0x4) { |
| 71 | /* 2666MHz */ |
| 72 | reg16 |= 0xad; |
| 73 | } else if (reg8 == 0) { |
| 74 | /* 3200MHz */ |
| 75 | reg16 |= 0xa0; |
| 76 | } else if (reg8 == 1) { |
| 77 | /* 4000MHz */ |
| 78 | reg16 |= 0xad; |
| 79 | } |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 80 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 81 | pci_write_config16(PCI_DEV(0,2,0), 0xcc, reg16); |
| 82 | |
| 83 | pci_write_config8(PCI_DEV(0,2,0), 0x62, |
| 84 | pci_read_config8(PCI_DEV(0,2,0), 0x62) & ~0x3); |
| 85 | pci_write_config8(PCI_DEV(0,2,0), 0x62, |
| 86 | pci_read_config8(PCI_DEV(0,2,0), 0x62) | 2); |
| 87 | |
| 88 | if (config->use_crt) { |
| 89 | /* Enable VGA */ |
| 90 | MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 15); |
| 91 | } else { |
| 92 | /* Disable VGA */ |
| 93 | MCHBAR32(0xb08) = MCHBAR32(0xb08) & ~(1 << 15); |
| 94 | } |
| 95 | |
| 96 | if (config->use_lvds) { |
| 97 | /* Enable LVDS */ |
| 98 | reg32 = MCHBAR32(0x3004); |
| 99 | reg32 &= ~0xf1000000; |
| 100 | reg32 |= 0x90000000; |
| 101 | MCHBAR32(0x3004) = reg32; |
| 102 | MCHBAR32(0x3008) = MCHBAR32(0x3008) | (1 << 9); |
| 103 | } else { |
| 104 | /* Disable LVDS */ |
| 105 | MCHBAR32(0xb08) = MCHBAR32(0xb08) | (3 << 25); |
| 106 | } |
| 107 | |
| 108 | MCHBAR32(0xff4) = 0x0c6db8b5f; |
| 109 | MCHBAR16(0xff8) = 0x24f; |
| 110 | |
| 111 | MCHBAR32(0xb08) = MCHBAR32(0xb08) & 0xffffff00; |
| 112 | MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 5); |
| 113 | |
| 114 | /* Legacy backlight control */ |
| 115 | pci_write_config8(PCI_DEV(0, 2, 0), 0xf4, 0x4c); |
| 116 | } |
| 117 | |
| 118 | static void early_misc_setup(void) |
| 119 | { |
Elyes HAOUAS | f00d373 | 2019-05-20 18:52:58 +0200 | [diff] [blame] | 120 | MCHBAR32(0x30); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 121 | MCHBAR32(0x30) = 0x21800; |
| 122 | DMIBAR32(0x2c) = 0x86000040; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 123 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); |
| 124 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 125 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 126 | early_graphics_setup(); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 127 | |
Elyes HAOUAS | f00d373 | 2019-05-20 18:52:58 +0200 | [diff] [blame] | 128 | MCHBAR32(0x40); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 129 | MCHBAR32(0x40) = 0x0; |
Elyes HAOUAS | f00d373 | 2019-05-20 18:52:58 +0200 | [diff] [blame] | 130 | MCHBAR32(0x40); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 131 | MCHBAR32(0x40) = 0x8; |
| 132 | |
| 133 | pci_write_config8(LPC, 0x8, 0x1d); |
| 134 | pci_write_config8(LPC, 0x8, 0x0); |
| 135 | RCBA32(0x3410) = 0x00020465; |
Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 136 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 137 | pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); |
| 138 | pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); |
| 139 | pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1); |
| 140 | pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1); |
| 141 | |
| 142 | RCBA32(0x3100) = 0x42210; |
| 143 | RCBA32(0x3108) = 0x10004321; |
| 144 | RCBA32(0x310c) = 0x00214321; |
| 145 | RCBA32(0x3110) = 0x1; |
| 146 | RCBA32(0x3140) = 0x01460132; |
| 147 | RCBA32(0x3142) = 0x02370146; |
| 148 | RCBA32(0x3144) = 0x32010237; |
| 149 | RCBA32(0x3146) = 0x01463201; |
| 150 | RCBA32(0x3148) = 0x146; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | static void pineview_setup_bars(void) |
| 154 | { |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 155 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 156 | pci_write_config8(D0F0, 0x8, 0x69); |
| 157 | |
| 158 | /* Set up all hardcoded northbridge BARs */ |
| 159 | pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1); |
| 160 | pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 161 | pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
| 162 | pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 163 | |
| 164 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 165 | pci_write_config8(D0F0, PAM0, 0x30); |
| 166 | pci_write_config8(D0F0, PAM1, 0x33); |
| 167 | pci_write_config8(D0F0, PAM2, 0x33); |
| 168 | pci_write_config8(D0F0, PAM3, 0x33); |
| 169 | pci_write_config8(D0F0, PAM4, 0x33); |
| 170 | pci_write_config8(D0F0, PAM5, 0x33); |
| 171 | pci_write_config8(D0F0, PAM6, 0x33); |
| 172 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 173 | printk(BIOS_DEBUG, " done.\n"); |
| 174 | } |
| 175 | |
| 176 | void pineview_early_initialization(void) |
| 177 | { |
| 178 | /* Print some chipset specific information */ |
| 179 | printk(BIOS_DEBUG, "Intel Pineview northbridge\n"); |
| 180 | |
| 181 | /* Setup all BARs required for early PCIe and raminit */ |
| 182 | pineview_setup_bars(); |
| 183 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 184 | /* Miscellaneous set up */ |
| 185 | early_misc_setup(); |
| 186 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 187 | /* Change port80 to LPC */ |
| 188 | RCBA32(GCS) &= (~0x04); |
| 189 | RCBA32(0x2010) |= (1 << 10); |
| 190 | } |