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Patrick Georgic49d7a32020-05-08 22:50:46 +02001## SPDX-License-Identifier: GPL-2.0-only
Ronald G. Minnich99451b12013-06-27 10:42:59 -07002
Ronald G. Minnich01ab2d12013-06-30 20:30:58 -07003config INTEL_DDI
4 bool
5 default n
6 help
7 helper functions for intel DDI operations
Vladimir Serbinenko1b12ef12014-02-21 07:21:00 +01008
9config INTEL_EDID
10 bool
11 default n
Vladimir Serbinenkoa2a906e2014-09-01 01:41:37 +020012
13config INTEL_INT15
14 bool
15 default n
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010016
17config INTEL_GMA_ACPI
18 bool
19 default n
Nico Huber542e9482016-10-05 17:47:32 +020020
Nico Huber612a8672019-02-19 19:11:29 +010021config INTEL_GMA_BCLV_OFFSET
22 hex
23 default 0xc8254
24
25config INTEL_GMA_BCLV_WIDTH
26 int
27 default 16
28
29config INTEL_GMA_BCLM_OFFSET
30 hex
31 default 0xc8256
32
33config INTEL_GMA_BCLM_WIDTH
34 int
35 default 16
36
Nico Huber561bebf2017-01-19 16:28:18 +010037config INTEL_GMA_SSC_ALTERNATE_REF
38 bool
39 default n
40 help
41 Set when the SSC reference clock for LVDS runs at a different fre-
42 quency than the general display reference clock.
43
44 To be set by northbridge or mainboard Kconfig. For most platforms,
45 there is no choice, i.e. for i945 and gm45 the SSC reference always
46 differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz
Angel Pons31b7ee42020-02-17 14:04:28 +010047 DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's
Nico Huber561bebf2017-01-19 16:28:18 +010048 the same frequency for SSC/non-SSC (120MHz). The only, currently
49 supported platform with a choice seems to be Pineview, where the
50 alternative is 100MHz vs. the default 96MHz.
51
Matt DeVillier681ef512018-02-11 01:17:01 -060052config INTEL_GMA_SWSMISCI
53 bool
54 default n
55 help
56 Select this option for Atom-based platforms which use the SWSMISCI
57 register (0xe0) rather than the SWSCI register (0xe8).
58
Nico Huberb92c4e32019-02-18 01:25:58 +010059config INTEL_GMA_LIBGFXINIT_EDID
60 bool
61
Srinidhi N Kaushik6719c822020-11-02 16:47:29 -080062config VBT_DATA_SIZE_KB
63 int
64 default 8
65
Arthur Heymansccdef192017-08-07 14:11:01 +020066config GFX_GMA_ANALOG_I2C_HDMI_B
67 bool
68
69config GFX_GMA_ANALOG_I2C_HDMI_C
70 bool
71
72config GFX_GMA_ANALOG_I2C_HDMI_D
73 bool
Nico Huber1e054352017-03-13 19:56:01 +010074
Angel Pons51e138c2020-07-16 00:56:27 +020075config GFX_GMA_IGNORE_PRESENCE_STRAPS
76 def_bool n
77 depends on MAINBOARD_HAS_LIBGFXINIT
78 help
79 libgfxinit uses the GPU presence straps to determine if a display port
80 is present/enabled. Select this option if a board doesn't correctly implement
81 these straps, causing libgfxinit to fail to detect an attached panel.
82
Nico Huber1e054352017-03-13 19:56:01 +010083config GFX_GMA
84 def_bool y
Nico Huberf2dd0492017-10-29 15:42:44 +010085 depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \
Angel Pons95de2312020-02-17 13:08:53 +010086 || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \
Angel Pons52bab252021-04-27 11:44:02 +020087 || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL \
88 || SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \
Angel Pons69007ec2021-04-27 22:28:42 +020089 || SOC_INTEL_CANNONLAKE_BASE
Nico Huberb92c4e32019-02-18 01:25:58 +010090 depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID
Nico Huberfde7c312019-02-18 01:16:22 +010091 select RAMSTAGE_LIBHWBASE
92
Jeremy Compostella765e5df2022-12-01 15:45:51 -070093config EARLY_GFX_GMA
94 def_bool y
95 depends on SOC_INTEL_ALDERLAKE
96 depends on MAINBOARD_USE_EARLY_LIBGFXINIT
97 select ROMSTAGE_LIBHWBASE
98
99config GFX_GMA_DEFAULT_MMIO
100 hex
101 depends on HWBASE_STATIC_MMIO && (GFX_GMA || EARLY_GFX_GMA)
102 help
103 Graphics device MMIO address. This is typically an unused
104 memory mapping region which can be allocated to the MMIO
105 region as graphics PCI device Base Address Range zero.
106
Nico Huber4ce52902020-02-15 17:56:01 +0100107config GFX_GMA_PANEL_1_ON_EDP
Nico Huberfde7c312019-02-18 01:16:22 +0100108 bool
Jeremy Compostella765e5df2022-12-01 15:45:51 -0700109 depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \
110 || MAINBOARD_HAS_EARLY_LIBGFXINIT
Nico Huber4ce52902020-02-15 17:56:01 +0100111 default n if GFX_GMA_PANEL_1_ON_LVDS
Nico Huberfde7c312019-02-18 01:16:22 +0100112 default y
113
Nico Huber4ce52902020-02-15 17:56:01 +0100114config GFX_GMA_PANEL_1_ON_LVDS
Nico Huberfde7c312019-02-18 01:16:22 +0100115 bool
Jeremy Compostella765e5df2022-12-01 15:45:51 -0700116 depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \
117 || MAINBOARD_HAS_EARLY_LIBGFXINIT
Angel Pons95de2312020-02-17 13:08:53 +0100118 default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE
Nico Huberfde7c312019-02-18 01:16:22 +0100119 default n
Nico Huber1e054352017-03-13 19:56:01 +0100120
Meera Ravindranath1b8159b2021-04-29 20:30:27 +0530121config INTEL_GMA_OPREGION_2_1
122 bool
123 default n
124
Jeremy Compostella765e5df2022-12-01 15:45:51 -0700125if GFX_GMA || EARLY_GFX_GMA
Nico Huber1e054352017-03-13 19:56:01 +0100126
Nico Huber47953d02019-05-10 16:26:07 +0200127config GFX_GMA_DYN_CPU
128 def_bool y
129 help
130 Activates runtime CPU detection in libgfxinit.
131
132config GFX_GMA_GENERATION
Nico Huber542e9482016-10-05 17:47:32 +0200133 string
Nico Huber628a3c52018-11-27 14:15:31 +0100134 default "Broxton" if SOC_INTEL_APOLLOLAKE
Angel Pons69007ec2021-04-27 22:28:42 +0200135 default "Skylake" if SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_CANNONLAKE_BASE
Nico Huber47953d02019-05-10 16:26:07 +0200136 default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
Angel Pons95de2312020-02-17 13:08:53 +0100137 default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE
Nico Huberf2dd0492017-10-29 15:42:44 +0100138 default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X
Jeremy Compostella44752632022-12-02 10:18:39 -0700139 default "Tigerlake" if SOC_INTEL_ALDERLAKE
Nico Huber542e9482016-10-05 17:47:32 +0200140
Nico Huber33940402020-12-20 03:27:36 +0100141config GFX_GMA_PCH
142 string
143 default "Ibex_Peak" if NORTHBRIDGE_INTEL_IRONLAKE
144 default "Cougar_Point" if NORTHBRIDGE_INTEL_SANDYBRIDGE
145 default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL
146 default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE
147 default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE
Jeremy Compostella44752632022-12-02 10:18:39 -0700148 default "Alder_Point" if SOC_INTEL_ALDERLAKE
Nico Huber33940402020-12-20 03:27:36 +0100149 default "No_PCH"
150
Nico Huber4ce52902020-02-15 17:56:01 +0100151config GFX_GMA_PANEL_1_PORT
Nico Huber542e9482016-10-05 17:47:32 +0200152 string
Nico Huber4ce52902020-02-15 17:56:01 +0100153 default "eDP" if GFX_GMA_PANEL_1_ON_EDP
Nico Huber542e9482016-10-05 17:47:32 +0200154 default "LVDS"
155
Nico Huber4ce52902020-02-15 17:56:01 +0100156config GFX_GMA_PANEL_2_PORT
157 string
158 default "Disabled"
159
Nico Huber542e9482016-10-05 17:47:32 +0200160config GFX_GMA_ANALOG_I2C_PORT
161 string
162 default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B
163 default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C
164 default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D
165 default "PCH_DAC"
166 help
167 Boards with a DVI-I connector share the I2C pins for both analog and
168 digital displays. In that case, the EDID for a VGA display has to be
169 read over the I2C interface of the coupled digital port.
Nico Huber1e054352017-03-13 19:56:01 +0100170
171endif