Patrick Georgi | c49d7a3 | 2020-05-08 22:50:46 +0200 | [diff] [blame] | 1 | ## SPDX-License-Identifier: GPL-2.0-only |
Ronald G. Minnich | 99451b1 | 2013-06-27 10:42:59 -0700 | [diff] [blame] | 2 | |
Ronald G. Minnich | 01ab2d1 | 2013-06-30 20:30:58 -0700 | [diff] [blame] | 3 | config INTEL_DDI |
| 4 | bool |
| 5 | default n |
| 6 | help |
| 7 | helper functions for intel DDI operations |
Vladimir Serbinenko | 1b12ef1 | 2014-02-21 07:21:00 +0100 | [diff] [blame] | 8 | |
| 9 | config INTEL_EDID |
| 10 | bool |
| 11 | default n |
Vladimir Serbinenko | a2a906e | 2014-09-01 01:41:37 +0200 | [diff] [blame] | 12 | |
| 13 | config INTEL_INT15 |
| 14 | bool |
| 15 | default n |
Vladimir Serbinenko | dd2bc3f | 2014-10-31 09:16:31 +0100 | [diff] [blame] | 16 | |
| 17 | config INTEL_GMA_ACPI |
| 18 | bool |
| 19 | default n |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 20 | |
Nico Huber | 612a867 | 2019-02-19 19:11:29 +0100 | [diff] [blame] | 21 | config INTEL_GMA_BCLV_OFFSET |
| 22 | hex |
| 23 | default 0xc8254 |
| 24 | |
| 25 | config INTEL_GMA_BCLV_WIDTH |
| 26 | int |
| 27 | default 16 |
| 28 | |
| 29 | config INTEL_GMA_BCLM_OFFSET |
| 30 | hex |
| 31 | default 0xc8256 |
| 32 | |
| 33 | config INTEL_GMA_BCLM_WIDTH |
| 34 | int |
| 35 | default 16 |
| 36 | |
Nico Huber | 561bebf | 2017-01-19 16:28:18 +0100 | [diff] [blame] | 37 | config INTEL_GMA_SSC_ALTERNATE_REF |
| 38 | bool |
| 39 | default n |
| 40 | help |
| 41 | Set when the SSC reference clock for LVDS runs at a different fre- |
| 42 | quency than the general display reference clock. |
| 43 | |
| 44 | To be set by northbridge or mainboard Kconfig. For most platforms, |
| 45 | there is no choice, i.e. for i945 and gm45 the SSC reference always |
| 46 | differs from the display reference clock (i945: 66Mhz SSC vs. 48MHz |
Angel Pons | 31b7ee4 | 2020-02-17 14:04:28 +0100 | [diff] [blame] | 47 | DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Arrandale and newer, it's |
Nico Huber | 561bebf | 2017-01-19 16:28:18 +0100 | [diff] [blame] | 48 | the same frequency for SSC/non-SSC (120MHz). The only, currently |
| 49 | supported platform with a choice seems to be Pineview, where the |
| 50 | alternative is 100MHz vs. the default 96MHz. |
| 51 | |
Matt DeVillier | 681ef51 | 2018-02-11 01:17:01 -0600 | [diff] [blame] | 52 | config INTEL_GMA_SWSMISCI |
| 53 | bool |
| 54 | default n |
| 55 | help |
| 56 | Select this option for Atom-based platforms which use the SWSMISCI |
| 57 | register (0xe0) rather than the SWSCI register (0xe8). |
| 58 | |
Nico Huber | b92c4e3 | 2019-02-18 01:25:58 +0100 | [diff] [blame] | 59 | config INTEL_GMA_LIBGFXINIT_EDID |
| 60 | bool |
| 61 | |
Srinidhi N Kaushik | 6719c82 | 2020-11-02 16:47:29 -0800 | [diff] [blame] | 62 | config VBT_DATA_SIZE_KB |
| 63 | int |
| 64 | default 8 |
| 65 | |
Arthur Heymans | ccdef19 | 2017-08-07 14:11:01 +0200 | [diff] [blame] | 66 | config GFX_GMA_ANALOG_I2C_HDMI_B |
| 67 | bool |
| 68 | |
| 69 | config GFX_GMA_ANALOG_I2C_HDMI_C |
| 70 | bool |
| 71 | |
| 72 | config GFX_GMA_ANALOG_I2C_HDMI_D |
| 73 | bool |
Nico Huber | 1e05435 | 2017-03-13 19:56:01 +0100 | [diff] [blame] | 74 | |
Angel Pons | 51e138c | 2020-07-16 00:56:27 +0200 | [diff] [blame] | 75 | config GFX_GMA_IGNORE_PRESENCE_STRAPS |
| 76 | def_bool n |
| 77 | depends on MAINBOARD_HAS_LIBGFXINIT |
| 78 | help |
| 79 | libgfxinit uses the GPU presence straps to determine if a display port |
| 80 | is present/enabled. Select this option if a board doesn't correctly implement |
| 81 | these straps, causing libgfxinit to fail to detect an attached panel. |
| 82 | |
Nico Huber | 1e05435 | 2017-03-13 19:56:01 +0100 | [diff] [blame] | 83 | config GFX_GMA |
| 84 | def_bool y |
Nico Huber | f2dd049 | 2017-10-29 15:42:44 +0100 | [diff] [blame] | 85 | depends on NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X \ |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 86 | || NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE \ |
Angel Pons | 52bab25 | 2021-04-27 11:44:02 +0200 | [diff] [blame] | 87 | || NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL \ |
| 88 | || SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_APOLLOLAKE \ |
Angel Pons | 69007ec | 2021-04-27 22:28:42 +0200 | [diff] [blame] | 89 | || SOC_INTEL_CANNONLAKE_BASE |
Nico Huber | b92c4e3 | 2019-02-18 01:25:58 +0100 | [diff] [blame] | 90 | depends on MAINBOARD_USE_LIBGFXINIT || INTEL_GMA_LIBGFXINIT_EDID |
Nico Huber | fde7c31 | 2019-02-18 01:16:22 +0100 | [diff] [blame] | 91 | select RAMSTAGE_LIBHWBASE |
| 92 | |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 93 | config EARLY_GFX_GMA |
| 94 | def_bool y |
| 95 | depends on SOC_INTEL_ALDERLAKE |
| 96 | depends on MAINBOARD_USE_EARLY_LIBGFXINIT |
| 97 | select ROMSTAGE_LIBHWBASE |
| 98 | |
| 99 | config GFX_GMA_DEFAULT_MMIO |
| 100 | hex |
| 101 | depends on HWBASE_STATIC_MMIO && (GFX_GMA || EARLY_GFX_GMA) |
| 102 | help |
| 103 | Graphics device MMIO address. This is typically an unused |
| 104 | memory mapping region which can be allocated to the MMIO |
| 105 | region as graphics PCI device Base Address Range zero. |
| 106 | |
Nico Huber | 4ce5290 | 2020-02-15 17:56:01 +0100 | [diff] [blame] | 107 | config GFX_GMA_PANEL_1_ON_EDP |
Nico Huber | fde7c31 | 2019-02-18 01:16:22 +0100 | [diff] [blame] | 108 | bool |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 109 | depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ |
| 110 | || MAINBOARD_HAS_EARLY_LIBGFXINIT |
Nico Huber | 4ce5290 | 2020-02-15 17:56:01 +0100 | [diff] [blame] | 111 | default n if GFX_GMA_PANEL_1_ON_LVDS |
Nico Huber | fde7c31 | 2019-02-18 01:16:22 +0100 | [diff] [blame] | 112 | default y |
| 113 | |
Nico Huber | 4ce5290 | 2020-02-15 17:56:01 +0100 | [diff] [blame] | 114 | config GFX_GMA_PANEL_1_ON_LVDS |
Nico Huber | fde7c31 | 2019-02-18 01:16:22 +0100 | [diff] [blame] | 115 | bool |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 116 | depends on GFX_GMA || MAINBOARD_HAS_LIBGFXINIT \ |
| 117 | || MAINBOARD_HAS_EARLY_LIBGFXINIT |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 118 | default y if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_IRONLAKE |
Nico Huber | fde7c31 | 2019-02-18 01:16:22 +0100 | [diff] [blame] | 119 | default n |
Nico Huber | 1e05435 | 2017-03-13 19:56:01 +0100 | [diff] [blame] | 120 | |
Meera Ravindranath | 1b8159b | 2021-04-29 20:30:27 +0530 | [diff] [blame] | 121 | config INTEL_GMA_OPREGION_2_1 |
| 122 | bool |
| 123 | default n |
| 124 | |
Jeremy Compostella | 765e5df | 2022-12-01 15:45:51 -0700 | [diff] [blame] | 125 | if GFX_GMA || EARLY_GFX_GMA |
Nico Huber | 1e05435 | 2017-03-13 19:56:01 +0100 | [diff] [blame] | 126 | |
Nico Huber | 47953d0 | 2019-05-10 16:26:07 +0200 | [diff] [blame] | 127 | config GFX_GMA_DYN_CPU |
| 128 | def_bool y |
| 129 | help |
| 130 | Activates runtime CPU detection in libgfxinit. |
| 131 | |
| 132 | config GFX_GMA_GENERATION |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 133 | string |
Nico Huber | 628a3c5 | 2018-11-27 14:15:31 +0100 | [diff] [blame] | 134 | default "Broxton" if SOC_INTEL_APOLLOLAKE |
Angel Pons | 69007ec | 2021-04-27 22:28:42 +0200 | [diff] [blame] | 135 | default "Skylake" if SOC_INTEL_COMMON_SKYLAKE_BASE || SOC_INTEL_CANNONLAKE_BASE |
Nico Huber | 47953d0 | 2019-05-10 16:26:07 +0200 | [diff] [blame] | 136 | default "Haswell" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 137 | default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE |
Nico Huber | f2dd049 | 2017-10-29 15:42:44 +0100 | [diff] [blame] | 138 | default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X |
Jeremy Compostella | 4475263 | 2022-12-02 10:18:39 -0700 | [diff] [blame] | 139 | default "Tigerlake" if SOC_INTEL_ALDERLAKE |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 140 | |
Nico Huber | 3394040 | 2020-12-20 03:27:36 +0100 | [diff] [blame] | 141 | config GFX_GMA_PCH |
| 142 | string |
| 143 | default "Ibex_Peak" if NORTHBRIDGE_INTEL_IRONLAKE |
| 144 | default "Cougar_Point" if NORTHBRIDGE_INTEL_SANDYBRIDGE |
| 145 | default "Lynx_Point" if NORTHBRIDGE_INTEL_HASWELL || SOC_INTEL_BROADWELL |
| 146 | default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE |
| 147 | default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE |
Jeremy Compostella | 4475263 | 2022-12-02 10:18:39 -0700 | [diff] [blame] | 148 | default "Alder_Point" if SOC_INTEL_ALDERLAKE |
Nico Huber | 3394040 | 2020-12-20 03:27:36 +0100 | [diff] [blame] | 149 | default "No_PCH" |
| 150 | |
Nico Huber | 4ce5290 | 2020-02-15 17:56:01 +0100 | [diff] [blame] | 151 | config GFX_GMA_PANEL_1_PORT |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 152 | string |
Nico Huber | 4ce5290 | 2020-02-15 17:56:01 +0100 | [diff] [blame] | 153 | default "eDP" if GFX_GMA_PANEL_1_ON_EDP |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 154 | default "LVDS" |
| 155 | |
Nico Huber | 4ce5290 | 2020-02-15 17:56:01 +0100 | [diff] [blame] | 156 | config GFX_GMA_PANEL_2_PORT |
| 157 | string |
| 158 | default "Disabled" |
| 159 | |
Nico Huber | 542e948 | 2016-10-05 17:47:32 +0200 | [diff] [blame] | 160 | config GFX_GMA_ANALOG_I2C_PORT |
| 161 | string |
| 162 | default "PCH_HDMI_B" if GFX_GMA_ANALOG_I2C_HDMI_B |
| 163 | default "PCH_HDMI_C" if GFX_GMA_ANALOG_I2C_HDMI_C |
| 164 | default "PCH_HDMI_D" if GFX_GMA_ANALOG_I2C_HDMI_D |
| 165 | default "PCH_DAC" |
| 166 | help |
| 167 | Boards with a DVI-I connector share the I2C pins for both analog and |
| 168 | digital displays. In that case, the EDID for a VGA display has to be |
| 169 | read over the I2C interface of the coupled digital port. |
Nico Huber | 1e05435 | 2017-03-13 19:56:01 +0100 | [diff] [blame] | 170 | |
| 171 | endif |