Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 2 | |
Felix Held | dd2f3fa | 2021-02-08 22:23:54 +0100 | [diff] [blame] | 3 | #include <amdblocks/cpu.h> |
Felix Held | f1093af | 2021-07-13 23:00:26 +0200 | [diff] [blame] | 4 | #include <amdblocks/mca.h> |
Felix Held | a5cdf75 | 2021-03-10 15:47:00 +0100 | [diff] [blame] | 5 | #include <amdblocks/reset.h> |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 6 | #include <amdblocks/smm.h> |
Felix Held | f142ba5 | 2021-04-22 18:26:43 +0200 | [diff] [blame] | 7 | #include <assert.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 8 | #include <cpu/cpu.h> |
| 9 | #include <cpu/x86/mp.h> |
| 10 | #include <cpu/x86/mtrr.h> |
| 11 | #include <cpu/x86/msr.h> |
Kyösti Mälkki | b2a5f0b | 2019-08-04 19:54:32 +0300 | [diff] [blame] | 12 | #include <cpu/x86/smm.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 13 | #include <cpu/x86/lapic.h> |
| 14 | #include <device/device.h> |
| 15 | #include <device/pci_ops.h> |
| 16 | #include <soc/pci_devs.h> |
| 17 | #include <soc/cpu.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 18 | #include <soc/smi.h> |
| 19 | #include <soc/iomap.h> |
| 20 | #include <console/console.h> |
Zheng Bao | 6ba591b | 2020-06-09 09:47:06 +0800 | [diff] [blame] | 21 | #include <cpu/amd/microcode.h> |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame^] | 22 | #include <types.h> |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 23 | |
Felix Held | f142ba5 | 2021-04-22 18:26:43 +0200 | [diff] [blame] | 24 | _Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " |
| 25 | "available cores, use the downcore_mode and disable_smt devicetree settings instead."); |
| 26 | |
Felix Held | 79f5feb | 2021-04-22 18:49:49 +0200 | [diff] [blame] | 27 | /* MP and SMM loading initialization. */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 28 | |
| 29 | /* |
| 30 | * Do essential initialization tasks before APs can be fired up - |
| 31 | * |
| 32 | * 1. Prevent race condition in MTRR solution. Enable MTRRs on the BSP. This |
| 33 | * creates the MTRR solution that the APs will use. Otherwise APs will try to |
| 34 | * apply the incomplete solution as the BSP is calculating it. |
| 35 | */ |
| 36 | static void pre_mp_init(void) |
| 37 | { |
Aaron Durbin | a2c045b | 2020-05-28 10:19:18 -0600 | [diff] [blame] | 38 | x86_setup_mtrrs_with_detect_no_above_4gb(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 39 | x86_mtrr_check(); |
| 40 | } |
| 41 | |
Kyösti Mälkki | 2fec3949 | 2020-07-01 15:59:20 +0300 | [diff] [blame] | 42 | static void post_mp_init(void) |
| 43 | { |
| 44 | global_smi_enable(); |
| 45 | apm_control(APM_CNT_SMMINFO); |
| 46 | } |
| 47 | |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 48 | static const struct mp_ops mp_ops = { |
| 49 | .pre_mp_init = pre_mp_init, |
| 50 | .get_cpu_count = get_cpu_count, |
| 51 | .get_smm_info = get_smm_info, |
Felix Held | bc13481 | 2021-02-10 02:26:10 +0100 | [diff] [blame] | 52 | .relocation_handler = smm_relocation_handler, |
Kyösti Mälkki | 2fec3949 | 2020-07-01 15:59:20 +0300 | [diff] [blame] | 53 | .post_mp_init = post_mp_init, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 54 | }; |
| 55 | |
Kyösti Mälkki | 79e12ab | 2020-05-31 09:21:07 +0300 | [diff] [blame] | 56 | void mp_init_cpus(struct bus *cpu_bus) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 57 | { |
| 58 | /* Clear for take-off */ |
Felix Held | d27ef5b | 2021-10-20 20:18:12 +0200 | [diff] [blame^] | 59 | if (mp_init_with_smm(cpu_bus, &mp_ops) != CB_SUCCESS) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 60 | printk(BIOS_ERR, "MP initialization failure.\n"); |
| 61 | |
Raul E Rangel | 93375f2 | 2020-06-05 15:48:21 -0600 | [diff] [blame] | 62 | /* pre_mp_init made the flash not cacheable. Reset to WP for performance. */ |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 63 | mtrr_use_temp_range(FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 64 | } |
| 65 | |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 66 | static void model_17_init(struct device *dev) |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 67 | { |
| 68 | check_mca(); |
| 69 | setup_lapic(); |
Chris Wang | e2497d0 | 2020-08-03 22:36:13 +0800 | [diff] [blame] | 70 | set_cstate_io_addr(); |
Zheng Bao | 6ba591b | 2020-06-09 09:47:06 +0800 | [diff] [blame] | 71 | |
| 72 | amd_update_microcode_from_cbfs(); |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 73 | } |
| 74 | |
| 75 | static struct device_operations cpu_dev_ops = { |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 76 | .init = model_17_init, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 77 | }; |
| 78 | |
| 79 | static struct cpu_device_id cpu_table[] = { |
Felix Held | 53c173e | 2020-11-05 17:24:18 +0100 | [diff] [blame] | 80 | { X86_VENDOR_AMD, RAVEN1_B0_CPUID}, |
Felix Held | ab114c9 | 2020-05-22 02:40:40 +0200 | [diff] [blame] | 81 | { X86_VENDOR_AMD, PICASSO_B0_CPUID }, |
| 82 | { X86_VENDOR_AMD, PICASSO_B1_CPUID }, |
| 83 | { X86_VENDOR_AMD, RAVEN2_A0_CPUID }, |
| 84 | { X86_VENDOR_AMD, RAVEN2_A1_CPUID }, |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 85 | { 0, 0 }, |
| 86 | }; |
| 87 | |
Marshall Dawson | 34c3056 | 2019-07-16 15:18:00 -0600 | [diff] [blame] | 88 | static const struct cpu_driver model_17 __cpu_driver = { |
Martin Roth | 5c354b9 | 2019-04-22 14:55:16 -0600 | [diff] [blame] | 89 | .ops = &cpu_dev_ops, |
| 90 | .id_table = cpu_table, |
| 91 | }; |