Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 2 | |
| 3 | #ifndef NORTHBRIDGE_INTEL_PINEVIEW_H |
| 4 | #define NORTHBRIDGE_INTEL_PINEVIEW_H |
| 5 | |
Angel Pons | d25e2f6 | 2020-09-15 00:48:16 +0200 | [diff] [blame^] | 6 | #include <northbridge/intel/pineview/memmap.h> |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 7 | #include <southbridge/intel/i82801gx/i82801gx.h> |
| 8 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 9 | #define BOOT_PATH_NORMAL 0 |
| 10 | #define BOOT_PATH_RESET 1 |
| 11 | #define BOOT_PATH_RESUME 2 |
| 12 | |
| 13 | #define SYSINFO_DIMM_NOT_POPULATED 0x00 |
| 14 | #define SYSINFO_DIMM_X16SS 0x01 |
| 15 | #define SYSINFO_DIMM_X16DS 0x02 |
| 16 | #define SYSINFO_DIMM_X8DS 0x05 |
| 17 | #define SYSINFO_DIMM_X8DDS 0x06 |
| 18 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 19 | /* Device 0:0.0 PCI configuration space (Host Bridge) */ |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 20 | #define HOST_BRIDGE PCI_DEV(0, 0, 0) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 21 | |
Angel Pons | 0ddc245 | 2020-07-22 11:40:46 +0200 | [diff] [blame] | 22 | #include "hostbridge_regs.h" |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 23 | |
| 24 | /* Device 0:1.0 PCI configuration space (PCI Express) */ |
| 25 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 26 | #define PEGSTS 0x214 /* 32 bits */ |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 27 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 28 | /* Device 0:2.0 PCI configuration space (Integrated Graphics Device) */ |
| 29 | #define GMCH_IGD PCI_DEV(0, 2, 0) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 30 | |
| 31 | #define GMADR 0x18 |
| 32 | #define GTTADR 0x1c |
| 33 | #define BSM 0x5c |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 34 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 35 | #define GPIO32(x) *((volatile u32 *)(DEFAULT_GPIOBASE + x)) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * MCHBAR |
| 39 | */ |
| 40 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 41 | #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) |
| 42 | #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) |
| 43 | #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + x))) /* FIXME: causes changes */ |
| 44 | #define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) |
| 45 | #define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) |
| 46 | #define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) |
| 47 | #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) |
| 48 | #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) |
| 49 | #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) |
| 50 | #define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) |
| 51 | #define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) |
| 52 | #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) |
| 53 | |
| 54 | /* As there are many registers, define them on a separate file */ |
| 55 | |
| 56 | #include "mchbar_regs.h" |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 57 | |
| 58 | /* |
| 59 | * EPBAR - Egress Port Root Complex Register Block |
| 60 | */ |
| 61 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 62 | #define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 63 | #define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) |
| 64 | #define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) |
| 65 | |
| 66 | /* |
| 67 | * DMIBAR |
| 68 | */ |
| 69 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 70 | #define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 71 | #define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) |
| 72 | #define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) |
| 73 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 74 | enum fsb_clk { |
| 75 | FSB_CLOCK_667MHz = 0, |
| 76 | FSB_CLOCK_800MHz = 1, |
| 77 | }; |
| 78 | |
| 79 | enum mem_clk { |
| 80 | MEM_CLOCK_667MHz = 0, |
| 81 | MEM_CLOCK_800MHz = 1, |
| 82 | }; |
| 83 | |
| 84 | enum ddr { |
| 85 | DDR2 = 2, |
| 86 | DDR3 = 3, |
| 87 | }; |
| 88 | |
| 89 | enum chip_width { /* as in DDR3 spd */ |
| 90 | CHIP_WIDTH_x4 = 0, |
| 91 | CHIP_WIDTH_x8 = 1, |
| 92 | CHIP_WIDTH_x16 = 2, |
| 93 | CHIP_WIDTH_x32 = 3, |
| 94 | }; |
| 95 | |
| 96 | enum chip_cap { /* as in DDR3 spd */ |
| 97 | CHIP_CAP_256M = 0, |
| 98 | CHIP_CAP_512M = 1, |
| 99 | CHIP_CAP_1G = 2, |
| 100 | CHIP_CAP_2G = 3, |
| 101 | CHIP_CAP_4G = 4, |
| 102 | CHIP_CAP_8G = 5, |
| 103 | CHIP_CAP_16G = 6, |
| 104 | }; |
| 105 | |
| 106 | struct timings { |
| 107 | unsigned int CAS; |
| 108 | enum fsb_clk fsb_clock; |
| 109 | enum mem_clk mem_clock; |
| 110 | unsigned int tRAS; |
| 111 | unsigned int tRP; |
| 112 | unsigned int tRCD; |
| 113 | unsigned int tWR; |
| 114 | unsigned int tRFC; |
| 115 | unsigned int tWTR; |
| 116 | unsigned int tRRD; |
| 117 | unsigned int tRTP; |
| 118 | }; |
| 119 | |
| 120 | struct dimminfo { |
| 121 | unsigned int card_type; /* 0x0: unpopulated, |
| 122 | 0xa - 0xf: raw card type A - F */ |
| 123 | u8 type; |
| 124 | enum chip_width width; |
| 125 | enum chip_cap chip_capacity; |
| 126 | unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ |
| 127 | unsigned int sides; |
| 128 | unsigned int banks; |
| 129 | unsigned int ranks; |
| 130 | unsigned int rows; |
| 131 | unsigned int cols; |
| 132 | unsigned int cas_latencies; |
| 133 | unsigned int tAAmin; |
| 134 | unsigned int tCKmin; |
| 135 | unsigned int tWR; |
| 136 | unsigned int tRP; |
| 137 | unsigned int tRCD; |
| 138 | unsigned int tRAS; |
Martin Roth | 128c104 | 2016-11-18 09:29:03 -0700 | [diff] [blame] | 139 | unsigned int rank_capacity_mb; /* per rank in Megabytes */ |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 140 | u8 spd_data[256]; |
| 141 | }; |
| 142 | |
| 143 | struct pllparam { |
| 144 | u8 kcoarse[2][72]; |
| 145 | u8 pi[2][72]; |
| 146 | u8 dben[2][72]; |
| 147 | u8 dbsel[2][72]; |
| 148 | u8 clkdelay[2][72]; |
| 149 | }; |
| 150 | |
| 151 | struct sysinfo { |
| 152 | u8 maxpi; |
| 153 | u8 pioffset; |
| 154 | u8 pi[8]; |
| 155 | u16 coarsectrl; |
| 156 | u16 coarsedelay; |
| 157 | u16 mediumphase; |
| 158 | u16 readptrdelay; |
| 159 | |
| 160 | int txt_enabled; |
| 161 | int cores; |
| 162 | int boot_path; |
| 163 | int max_ddr2_mhz; |
| 164 | int max_ddr3_mt; |
| 165 | int max_fsb_mhz; |
| 166 | int max_render_mhz; |
| 167 | int enable_igd; |
| 168 | int enable_peg; |
| 169 | u16 ggc; |
| 170 | |
| 171 | int dimm_config[2]; |
| 172 | int dimms_per_ch; |
| 173 | int spd_type; |
| 174 | int channel_capacity[2]; |
| 175 | struct timings selected_timings; |
| 176 | struct dimminfo dimms[4]; |
| 177 | u8 spd_map[4]; |
| 178 | |
| 179 | u8 nodll; |
| 180 | u8 async; |
| 181 | u8 dt0mode; |
| 182 | u8 mvco4x; /* 0 (8x) or 1 (4x) */ |
| 183 | }; |
| 184 | |
Angel Pons | 39ff703 | 2020-03-09 21:39:44 +0100 | [diff] [blame] | 185 | void pineview_early_init(void); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 186 | u32 decode_igd_memory_size(const u32 gms); |
| 187 | u32 decode_igd_gtt_size(const u32 gsm); |
Angel Pons | 653d871 | 2020-08-03 15:40:54 +0200 | [diff] [blame] | 188 | int decode_pcie_bar(u32 *const base, u32 *const len); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 189 | |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 190 | /* Mainboard romstage callback functions */ |
Arthur Heymans | c6ff1ac | 2019-01-11 16:06:19 +0100 | [diff] [blame] | 191 | void get_mb_spd_addrmap(u8 *spd_addr_map); |
| 192 | void mb_pirq_setup(void); /* optional */ |
| 193 | |
Damien Zammit | 6247793 | 2015-05-03 21:34:38 +1000 | [diff] [blame] | 194 | #endif /* NORTHBRIDGE_INTEL_PINEVIEW_H */ |