Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 2 | |
| 3 | #include <console/console.h> |
| 4 | #include <device/device.h> |
| 5 | #include <device/pci.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 7 | #include <device/pci_ids.h> |
Arthur Heymans | 742df5a | 2019-06-03 16:24:41 +0200 | [diff] [blame] | 8 | #include "chip.h" |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 9 | #include "i82801gx.h" |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 10 | #include "sata.h" |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 11 | |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 12 | static u8 get_ich7_sata_ports(void) |
| 13 | { |
| 14 | struct device *lpc; |
| 15 | |
Kyösti Mälkki | c70eed1 | 2018-05-22 02:18:00 +0300 | [diff] [blame] | 16 | lpc = pcidev_on_root(31, 0); |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 17 | |
| 18 | switch (pci_read_config16(lpc, PCI_DEVICE_ID)) { |
| 19 | case 0x27b0: |
| 20 | case 0x27b8: |
| 21 | return 0xf; |
| 22 | case 0x27b9: |
| 23 | case 0x27bd: |
| 24 | return 0x5; |
| 25 | case 0x27bc: |
| 26 | return 0x3; |
| 27 | default: |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 28 | printk(BIOS_ERR, "i82801gx_sata: error: cannot determine port config\n"); |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 29 | return 0; |
| 30 | } |
| 31 | } |
| 32 | |
| 33 | void sata_enable(struct device *dev) |
| 34 | { |
| 35 | /* Get the chip configuration */ |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 36 | struct southbridge_intel_i82801gx_config *config = dev->chip_info; |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 37 | |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 38 | if (config->sata_mode == SATA_MODE_AHCI) { |
| 39 | /* Check if the southbridge supports AHCI */ |
| 40 | struct device *lpc_dev = pcidev_on_root(31, 0); |
| 41 | if (!lpc_dev) { |
| 42 | /* According to the PCI spec function 0 on a bus:device |
| 43 | needs to be active for other functions to be enabled. |
| 44 | Since SATA is on the same bus:device as the LPC |
| 45 | bridge, it makes little sense to continue. */ |
| 46 | die("Couldn't find the LPC device!\n"); |
| 47 | } |
| 48 | |
| 49 | const bool ahci_supported = !(pci_read_config32(lpc_dev, FDVCT) |
| 50 | & AHCI_UNSUPPORTED); |
| 51 | |
| 52 | if (!ahci_supported) { |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 53 | /* Fallback to IDE PLAIN for sata for the rest of the initialization */ |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 54 | config->sata_mode = SATA_MODE_IDE_PLAIN; |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 55 | printk(BIOS_DEBUG, "AHCI not supported, falling back to plain mode.\n"); |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 56 | } |
| 57 | |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 58 | } |
| 59 | |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 60 | if (config->sata_mode == SATA_MODE_AHCI) { |
| 61 | /* Set map to ahci */ |
| 62 | pci_write_config8(dev, SATA_MAP, |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 63 | (pci_read_config8(dev, SATA_MAP) & ~0xc3) | 0x40); |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 64 | } else { |
| 65 | /* Set map to ide */ |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 66 | pci_write_config8(dev, SATA_MAP, pci_read_config8(dev, SATA_MAP) & ~0xc3); |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 67 | } |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 68 | /* At this point, the new pci id will appear on the bus */ |
| 69 | } |
| 70 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 71 | static void sata_init(struct device *dev) |
| 72 | { |
| 73 | u32 reg32; |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 74 | u16 reg16; |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 75 | u8 ports; |
Sven Schnelle | b2f173e | 2011-10-27 13:05:40 +0200 | [diff] [blame] | 76 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 77 | /* Get the chip configuration */ |
Elyes HAOUAS | 8d9a6f1 | 2020-04-28 04:57:27 +0200 | [diff] [blame] | 78 | const struct southbridge_intel_i82801gx_config *config = dev->chip_info; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 79 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 80 | printk(BIOS_DEBUG, "i82801gx_sata: initializing...\n"); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 81 | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 82 | if (config == NULL) { |
Uwe Hermann | 607614d | 2010-11-18 20:12:13 +0000 | [diff] [blame] | 83 | printk(BIOS_ERR, "i82801gx_sata: error: device not in devicetree.cb!\n"); |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 84 | return; |
| 85 | } |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 86 | |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 87 | /* Get ICH7 SATA port config */ |
| 88 | ports = get_ich7_sata_ports(); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 89 | |
| 90 | /* Enable BARs */ |
Angel Pons | 89739ba | 2020-07-25 02:46:39 +0200 | [diff] [blame] | 91 | pci_write_config16(dev, PCI_COMMAND, |
| 92 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 93 | |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 94 | switch (config->sata_mode) { |
| 95 | case SATA_MODE_IDE_LEGACY_COMBINED: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 96 | printk(BIOS_DEBUG, "SATA controller in combined mode.\n"); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 97 | /* No AHCI: clear AHCI base */ |
Petr Cvek | c49869b | 2019-10-01 04:01:21 +0200 | [diff] [blame] | 98 | pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 99 | /* And without AHCI BAR no memory decoding */ |
| 100 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 101 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 102 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 103 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 104 | pci_write_config8(dev, 0x09, 0x80); |
| 105 | |
| 106 | /* Set timings */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 107 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 108 | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); |
| 109 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
| 110 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 111 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 112 | |
| 113 | /* Sync DMA */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 114 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); |
| 115 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 116 | |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 117 | /* Set IDE I/O Configuration */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 118 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 119 | pci_write_config32(dev, IDE_CONFIG, reg32); |
| 120 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 121 | /* Combine IDE - SATA configuration */ |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 122 | pci_write_config8(dev, SATA_MAP, 0x02); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 123 | |
Damien Zammit | 1533f13 | 2016-01-16 02:52:53 +1100 | [diff] [blame] | 124 | /* Restrict ports - 0 and 2 only available */ |
| 125 | ports &= 0x5; |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 126 | break; |
| 127 | case SATA_MODE_AHCI: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 128 | printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n"); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 129 | /* Allow both Legacy and Native mode */ |
| 130 | pci_write_config8(dev, 0x09, 0x8f); |
| 131 | |
| 132 | /* Set Interrupt Line */ |
| 133 | /* Interrupt Pin is set by D31IP.PIP */ |
| 134 | pci_write_config8(dev, INTR_LN, 0x0a); |
| 135 | |
Petr Cvek | c49869b | 2019-10-01 04:01:21 +0200 | [diff] [blame] | 136 | struct resource *ahci_res = find_resource(dev, PCI_BASE_ADDRESS_5); |
| 137 | if (ahci_res != NULL) |
| 138 | /* write AHCI GHC_PI register */ |
Elyes HAOUAS | 92646ea | 2020-04-04 13:43:03 +0200 | [diff] [blame] | 139 | write32(res2mmio(ahci_res, 0xc, 0), config->sata_ports_implemented); |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 140 | break; |
| 141 | default: |
| 142 | case SATA_MODE_IDE_PLAIN: |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 143 | printk(BIOS_DEBUG, "SATA controller in plain mode.\n"); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 144 | /* Set Sata Controller Mode. No Mapping(?) */ |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 145 | pci_write_config8(dev, SATA_MAP, 0x00); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 146 | |
| 147 | /* No AHCI: clear AHCI base */ |
Petr Cvek | c49869b | 2019-10-01 04:01:21 +0200 | [diff] [blame] | 148 | pci_write_config32(dev, PCI_BASE_ADDRESS_5, 0x00000000); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 149 | |
| 150 | /* And without AHCI BAR no memory decoding */ |
| 151 | reg16 = pci_read_config16(dev, PCI_COMMAND); |
| 152 | reg16 &= ~PCI_COMMAND_MEMORY; |
| 153 | pci_write_config16(dev, PCI_COMMAND, reg16); |
| 154 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 155 | /* Native mode capable on both primary and secondary (0xa) |
| 156 | * or'ed with enabled (0x50) = 0xf |
| 157 | */ |
| 158 | pci_write_config8(dev, 0x09, 0x8f); |
| 159 | |
| 160 | /* Set Interrupt Line */ |
| 161 | /* Interrupt Pin is set by D31IP.PIP */ |
| 162 | pci_write_config8(dev, INTR_LN, 0xff); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 163 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 164 | /* Set timings */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 165 | pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | |
| 166 | IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | |
| 167 | IDE_PPE0 | IDE_IE0 | IDE_TIME0); |
| 168 | pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 169 | IDE_SITRE | IDE_ISP_3_CLOCKS | |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 170 | IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 171 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 172 | /* Sync DMA */ |
Stefan Reinauer | 573f7d4 | 2009-07-21 21:50:34 +0000 | [diff] [blame] | 173 | pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); |
| 174 | pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); |
Stefan Reinauer | 109ab31 | 2009-08-12 16:08:05 +0000 | [diff] [blame] | 175 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 176 | /* Set IDE I/O Configuration */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 177 | reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 178 | pci_write_config32(dev, IDE_CONFIG, reg32); |
Arthur Heymans | 5eb81be | 2019-01-10 23:13:11 +0100 | [diff] [blame] | 179 | break; |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 180 | } |
| 181 | |
Damien Zammit | 1533f13 | 2016-01-16 02:52:53 +1100 | [diff] [blame] | 182 | /* Set port control */ |
| 183 | pci_write_config8(dev, SATA_PCS, ports); |
| 184 | |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 185 | /* Enable clock gating for unused ports and set initialization reg */ |
| 186 | pci_write_config32(dev, SATA_IR, SIF3(ports) | SIF2 | SIF1 | SCRE); |
| 187 | |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 188 | /* All configurations need this SATA initialization sequence */ |
| 189 | pci_write_config8(dev, 0xa0, 0x40); |
| 190 | pci_write_config8(dev, 0xa6, 0x22); |
| 191 | pci_write_config8(dev, 0xa0, 0x78); |
| 192 | pci_write_config8(dev, 0xa6, 0x22); |
| 193 | pci_write_config8(dev, 0xa0, 0x88); |
| 194 | reg32 = pci_read_config32(dev, 0xa4); |
| 195 | reg32 &= 0xc0c0c0c0; |
| 196 | reg32 |= 0x1b1b1212; |
| 197 | pci_write_config32(dev, 0xa4, reg32); |
| 198 | pci_write_config8(dev, 0xa0, 0x8c); |
| 199 | reg32 = pci_read_config32(dev, 0xa4); |
| 200 | reg32 &= 0xc0c0ff00; |
| 201 | reg32 |= 0x121200aa; |
| 202 | pci_write_config32(dev, 0xa4, reg32); |
| 203 | pci_write_config8(dev, 0xa0, 0x00); |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 204 | |
| 205 | pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); |
Stefan Reinauer | a8e1168 | 2009-03-11 14:54:18 +0000 | [diff] [blame] | 206 | |
| 207 | /* Sata Initialization Register */ |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 208 | reg32 = pci_read_config32(dev, SATA_IR); |
| 209 | reg32 |= SCRD; // due to some bug |
| 210 | pci_write_config32(dev, SATA_IR, reg32); |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 211 | } |
| 212 | |
| 213 | static struct device_operations sata_ops = { |
| 214 | .read_resources = pci_dev_read_resources, |
| 215 | .set_resources = pci_dev_set_resources, |
| 216 | .enable_resources = pci_dev_enable_resources, |
| 217 | .init = sata_init, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 218 | .enable = i82801gx_enable, |
Angel Pons | 1fc0edd | 2020-05-31 00:03:28 +0200 | [diff] [blame] | 219 | .ops_pci = &pci_dev_ops_pci, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 220 | }; |
| 221 | |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 222 | static const unsigned short sata_ids[] = { |
| 223 | 0x27c0, /* Desktop Non-AHCI and Non-RAID Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 224 | 0x27c1, /* Desktop AHCI Mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 225 | 0x27c4, /* Mobile Non-AHCI and Non-RAID Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 226 | 0x27c5, /* Mobile AHCI Mode: 82801GBM/GHM (ICH7-M/ICH7-M DH) */ |
Damien Zammit | 647e385 | 2016-01-15 13:44:53 +1100 | [diff] [blame] | 227 | /* NOTE: Any of the below are not properly supported yet. */ |
| 228 | 0x27c3, /* Desktop RAID mode: 82801GB/GR/GDH (ICH7/ICH7R/ICH7DH) */ |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 229 | 0x27c6, /* ICH7M DH Raid Mode: 82801GHM (ICH7-M DH) */ |
| 230 | 0 |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 231 | }; |
| 232 | |
Patrick Georgi | efff733 | 2012-07-26 19:48:23 +0200 | [diff] [blame] | 233 | static const struct pci_driver i82801gx_sata_driver __pci_driver = { |
Arthur Heymans | 3f111b0 | 2017-03-09 12:02:52 +0100 | [diff] [blame] | 234 | .ops = &sata_ops, |
| 235 | .vendor = PCI_VENDOR_ID_INTEL, |
| 236 | .devices = sata_ids, |
Stefan Reinauer | debb11f | 2008-10-29 04:46:52 +0000 | [diff] [blame] | 237 | }; |