Intel ICH7 updates
- code restructuring (move ich7 out of i945)
- ACPI fixes
- major SMI handler updates
- make sure SMBus lives where we expect it
- try to get usb debug working
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/southbridge/intel/i82801gx/i82801gx_sata.c b/src/southbridge/intel/i82801gx/i82801gx_sata.c
index 0f092e9..74ba823 100644
--- a/src/southbridge/intel/i82801gx/i82801gx_sata.c
+++ b/src/southbridge/intel/i82801gx/i82801gx_sata.c
@@ -35,8 +35,10 @@
printk_debug("i82801gx_sata: initializing...\n");
- if (config == NULL)
+ if (config == NULL) {
printk_err("i82801gx_sata: error: device not in Config.lb!\n");
+ return;
+ }
/* SATA configuration */
@@ -55,12 +57,15 @@
pci_write_config8(dev, 0x09, 0x80);
/* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, 0x8000);
- pci_write_config16(dev, IDE_TIM_SEC, 0xa307);
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
/* Sync DMA */
- pci_write_config16(dev, 0x48, 0x0004);
- pci_write_config16(dev, 0x4a, 0x0200);
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
@@ -84,12 +89,15 @@
pci_write_config8(dev, INTR_LN, 0x0a);
/* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, 0xa307);
- pci_write_config16(dev, IDE_TIM_SEC, 0x8000);
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
/* Sync DMA */
- pci_write_config16(dev, 0x48, 0x0001);
- pci_write_config16(dev, 0x4a, 0x0001);
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
@@ -126,12 +134,16 @@
pci_write_config8(dev, INTR_LN, 0xff);
/* Set timings */
- pci_write_config16(dev, IDE_TIM_PRI, 0xa307);
- pci_write_config16(dev, IDE_TIM_SEC, 0xe303);
+ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+ IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+ IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+ pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+ IDE_SITRE | IDE_ISP_3_CLOCKS |
+ IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
/* Sync DMA */
- pci_write_config16(dev, 0x48, 0x0005);
- pci_write_config16(dev, 0x4a, 0x0201);
+ pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+ pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
/* Set IDE I/O Configuration */
reg32 = SIG_MODE_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;