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review.coreboot.org / coreboot / 8f86fa0da17a7f5ec981fdf09ebb2c6a3c17b2f6 / . / src / southbridge / amd / pi / hudson / sm.c
blob: c40bf5e1c9796956114b2676e6f00561c2945dc1 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]2
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]3#include <device/device.h>
4#include <device/pci.h>
5#include <device/pci_ids.h>
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]6#include <device/smbus.h>
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]7#include <arch/ioapic.h>
Kyösti Mälkki8f86fa02022-12-05 19:31:01 +0200[diff] [blame^]8#include <southbridge/amd/pi/hudson/ioapic.h>
Elyes HAOUAS400f9ca2019-06-23 07:01:22 +0200[diff] [blame]9
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]10#include "hudson.h"
11#include "smbus.c"
12
13#define NMI_OFF 0
14
15#define MAINBOARD_POWER_OFF 0
16#define MAINBOARD_POWER_ON 1
17
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]18/*
19* HUDSON enables all USB controllers by default in SMBUS Control.
20* HUDSON enables SATA by default in SMBUS Control.
21*/
22
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]23static void sm_init(struct device *dev)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]24{
Kyösti Mälkki8f86fa02022-12-05 19:31:01 +0200[diff] [blame^]25 setup_ioapic(VIO_APIC_VADDR, FCH_IOAPIC_ID);
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]26}
27
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]28static int lsmbus_recv_byte(struct device *dev)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]29{
30 u32 device;
31 struct resource *res;
32 struct bus *pbus;
33
34 device = dev->path.i2c.device;
35 pbus = get_pbus_smbus(dev);
36
37 res = find_resource(pbus->dev, 0x90);
38
39 return do_smbus_recv_byte(res->base, device);
40}
41
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]42static int lsmbus_send_byte(struct device *dev, u8 val)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]43{
44 u32 device;
45 struct resource *res;
46 struct bus *pbus;
47
48 device = dev->path.i2c.device;
49 pbus = get_pbus_smbus(dev);
50
51 res = find_resource(pbus->dev, 0x90);
52
53 return do_smbus_send_byte(res->base, device, val);
54}
55
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]56static int lsmbus_read_byte(struct device *dev, u8 address)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]57{
58 u32 device;
59 struct resource *res;
60 struct bus *pbus;
61
62 device = dev->path.i2c.device;
63 pbus = get_pbus_smbus(dev);
64
65 res = find_resource(pbus->dev, 0x90);
66
67 return do_smbus_read_byte(res->base, device, address);
68}
69
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]70static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]71{
72 u32 device;
73 struct resource *res;
74 struct bus *pbus;
75
76 device = dev->path.i2c.device;
77 pbus = get_pbus_smbus(dev);
78
79 res = find_resource(pbus->dev, 0x90);
80
81 return do_smbus_write_byte(res->base, device, address, val);
82}
83static struct smbus_bus_operations lops_smbus_bus = {
84 .recv_byte = lsmbus_recv_byte,
85 .send_byte = lsmbus_send_byte,
86 .read_byte = lsmbus_read_byte,
87 .write_byte = lsmbus_write_byte,
88};
89
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]90static void hudson_sm_read_resources(struct device *dev)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]91{
92}
93
94static void hudson_sm_set_resources(struct device *dev)
95{
96}
97
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]98static struct device_operations smbus_ops = {
99 .read_resources = hudson_sm_read_resources,
100 .set_resources = hudson_sm_set_resources,
101 .enable_resources = pci_dev_enable_resources,
102 .init = sm_init,
Kyösti Mälkkid0e212c2015-02-26 20:47:47 +0200[diff] [blame]103 .scan_bus = scan_smbus,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200[diff] [blame]104 .ops_pci = &pci_dev_ops_pci,
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]105 .ops_smbus_bus = &lops_smbus_bus,
106};
107static const struct pci_driver smbus_driver __pci_driver = {
108 .ops = &smbus_ops,
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]109 .vendor = PCI_VID_AMD,
Felix Held43cf27d2021-10-27 18:31:16 +0200[diff] [blame]110 /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame]111 .device = PCI_DID_AMD_SB900_SM,
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]112};