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review.coreboot.org / coreboot / 43b7f416783ccc98952a4eb5f9274907442b03e5 / . / src / southbridge / amd / pi / hudson / sm.c
blob: 79d1005997528b4a63c12e484d887baa4b4f7a15 [file] [log] [blame]
Angel Pons182dbde2020-04-02 23:49:05 +0200[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0-only */
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]2
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]3#include <device/device.h>
4#include <device/pci.h>
5#include <device/pci_ids.h>
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]6#include <device/smbus.h>
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]7#include <arch/ioapic.h>
Elyes HAOUAS400f9ca2019-06-23 07:01:22 +0200[diff] [blame]8
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]9#include "hudson.h"
10#include "smbus.c"
11
12#define NMI_OFF 0
13
14#define MAINBOARD_POWER_OFF 0
15#define MAINBOARD_POWER_ON 1
16
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]17/*
18* HUDSON enables all USB controllers by default in SMBUS Control.
19* HUDSON enables SATA by default in SMBUS Control.
20*/
21
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]22static void sm_init(struct device *dev)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]23{
Kevin Paul Herbertbde6d302014-12-24 18:43:20 -0800[diff] [blame]24 setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]25}
26
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]27static int lsmbus_recv_byte(struct device *dev)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]28{
29 u32 device;
30 struct resource *res;
31 struct bus *pbus;
32
33 device = dev->path.i2c.device;
34 pbus = get_pbus_smbus(dev);
35
36 res = find_resource(pbus->dev, 0x90);
37
38 return do_smbus_recv_byte(res->base, device);
39}
40
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]41static int lsmbus_send_byte(struct device *dev, u8 val)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]42{
43 u32 device;
44 struct resource *res;
45 struct bus *pbus;
46
47 device = dev->path.i2c.device;
48 pbus = get_pbus_smbus(dev);
49
50 res = find_resource(pbus->dev, 0x90);
51
52 return do_smbus_send_byte(res->base, device, val);
53}
54
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]55static int lsmbus_read_byte(struct device *dev, u8 address)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]56{
57 u32 device;
58 struct resource *res;
59 struct bus *pbus;
60
61 device = dev->path.i2c.device;
62 pbus = get_pbus_smbus(dev);
63
64 res = find_resource(pbus->dev, 0x90);
65
66 return do_smbus_read_byte(res->base, device, address);
67}
68
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]69static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]70{
71 u32 device;
72 struct resource *res;
73 struct bus *pbus;
74
75 device = dev->path.i2c.device;
76 pbus = get_pbus_smbus(dev);
77
78 res = find_resource(pbus->dev, 0x90);
79
80 return do_smbus_write_byte(res->base, device, address, val);
81}
82static struct smbus_bus_operations lops_smbus_bus = {
83 .recv_byte = lsmbus_recv_byte,
84 .send_byte = lsmbus_send_byte,
85 .read_byte = lsmbus_read_byte,
86 .write_byte = lsmbus_write_byte,
87};
88
Elyes HAOUASd9ef5462018-05-19 17:08:23 +0200[diff] [blame]89static void hudson_sm_read_resources(struct device *dev)
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]90{
91}
92
93static void hudson_sm_set_resources(struct device *dev)
94{
95}
96
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]97static struct device_operations smbus_ops = {
98 .read_resources = hudson_sm_read_resources,
99 .set_resources = hudson_sm_set_resources,
100 .enable_resources = pci_dev_enable_resources,
101 .init = sm_init,
Kyösti Mälkkid0e212c2015-02-26 20:47:47 +0200[diff] [blame]102 .scan_bus = scan_smbus,
Angel Pons1fc0edd2020-05-31 00:03:28 +0200[diff] [blame]103 .ops_pci = &pci_dev_ops_pci,
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]104 .ops_smbus_bus = &lops_smbus_bus,
105};
106static const struct pci_driver smbus_driver __pci_driver = {
107 .ops = &smbus_ops,
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]108 .vendor = PCI_VID_AMD,
Felix Held43cf27d2021-10-27 18:31:16 +0200[diff] [blame]109 /* PCI device ID is used on all discrete FCHs and Family 16h Models 00h-3Fh */
Felix Singer43b7f412022-03-07 04:34:52 +0100[diff] [blame^]110 .device = PCI_DID_AMD_SB900_SM,
Kyösti Mälkkie8b4da22014-10-21 18:22:32 +0300[diff] [blame]111};