Angel Pons | 16f6aa8 | 2020-04-05 15:47:21 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 2 | |
| 3 | /* |
| 4 | * This file is created based on Intel Tiger Lake Processor PCH Datasheet |
| 5 | * Document number: 575857 |
| 6 | * Chapter number: 2, 3, 4, 27, 28 |
| 7 | */ |
| 8 | |
Aamir Bohra | 5349044 | 2019-12-16 17:49:13 +0530 | [diff] [blame] | 9 | #include <console/console.h> |
| 10 | #include <console/post_codes.h> |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 11 | #include <device/mmio.h> |
| 12 | #include <device/device.h> |
| 13 | #include <device/pci_ops.h> |
| 14 | #include <intelblocks/fast_spi.h> |
| 15 | #include <intelblocks/gspi.h> |
| 16 | #include <intelblocks/lpc_lib.h> |
| 17 | #include <intelblocks/p2sb.h> |
| 18 | #include <intelblocks/pcr.h> |
| 19 | #include <intelblocks/pmclib.h> |
| 20 | #include <intelblocks/rtc.h> |
| 21 | #include <soc/bootblock.h> |
Aamir Bohra | 5349044 | 2019-12-16 17:49:13 +0530 | [diff] [blame] | 22 | #include <soc/espi.h> |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 23 | #include <soc/iomap.h> |
| 24 | #include <soc/p2sb.h> |
| 25 | #include <soc/pch.h> |
| 26 | #include <soc/pci_devs.h> |
| 27 | #include <soc/pcr_ids.h> |
| 28 | #include <soc/pm.h> |
| 29 | |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 30 | #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 31 | #define PCR_PSFX_TO_SHDW_BAR0 0 |
| 32 | #define PCR_PSFX_TO_SHDW_BAR1 0x4 |
| 33 | #define PCR_PSFX_TO_SHDW_BAR2 0x8 |
| 34 | #define PCR_PSFX_TO_SHDW_BAR3 0xC |
| 35 | #define PCR_PSFX_TO_SHDW_BAR4 0x10 |
| 36 | #define PCR_PSFX_TO_SHDW_PCIEN_IOEN 0x01 |
| 37 | #define PCR_PSFX_T0_SHDW_PCIEN 0x1C |
| 38 | |
| 39 | #define PCR_DMI_DMICTL 0x2234 |
| 40 | #define PCR_DMI_DMICTL_SRLOCK (1 << 31) |
| 41 | |
| 42 | #define PCR_DMI_ACPIBA 0x27B4 |
| 43 | #define PCR_DMI_ACPIBDID 0x27B8 |
| 44 | #define PCR_DMI_PMBASEA 0x27AC |
| 45 | #define PCR_DMI_PMBASEC 0x27B0 |
| 46 | |
| 47 | #define PCR_DMI_LPCIOD 0x2770 |
| 48 | #define PCR_DMI_LPCIOE 0x2774 |
| 49 | |
| 50 | static void soc_config_pwrmbase(void) |
| 51 | { |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 52 | /* |
| 53 | * Assign Resources to PWRMBASE |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 54 | * Clear BIT 1-2 Command Register |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 55 | */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 56 | pci_and_config16(PCH_DEV_PMC, PCI_COMMAND, ~(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 57 | |
| 58 | /* Program PWRM Base */ |
| 59 | pci_write_config32(PCH_DEV_PMC, PWRMBASE, PCH_PWRM_BASE_ADDRESS); |
| 60 | |
| 61 | /* Enable Bus Master and MMIO Space */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 62 | pci_or_config16(PCH_DEV_PMC, PCI_COMMAND, (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER)); |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 63 | |
| 64 | /* Enable PWRM in PMC */ |
Subrata Banik | 45caf97 | 2020-08-05 13:30:30 +0530 | [diff] [blame] | 65 | setbits32((void *) PCH_PWRM_BASE_ADDRESS + ACTL, PWRM_EN); |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | void bootblock_pch_early_init(void) |
| 69 | { |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame^] | 70 | /* |
| 71 | * Perform P2SB configuration before any another controller initialization as the |
| 72 | * controller might want to perform PCR settings. |
| 73 | */ |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 74 | p2sb_enable_bar(); |
| 75 | p2sb_configure_hpet(); |
| 76 | |
Furquan Shaikh | d149bfa | 2020-11-22 20:00:28 -0800 | [diff] [blame^] | 77 | fast_spi_early_init(SPI_BASE_ADDRESS); |
| 78 | gspi_early_bar_init(); |
| 79 | |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 80 | /* |
| 81 | * Enabling PWRM Base for accessing |
| 82 | * Global Reset Cause Register. |
| 83 | */ |
| 84 | soc_config_pwrmbase(); |
| 85 | } |
| 86 | |
| 87 | static void soc_config_acpibase(void) |
| 88 | { |
| 89 | uint32_t pmc_reg_value; |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 90 | uint32_t pmc_base_reg = PCR_PSF3_TO_SHDW_PMC_REG_BASE; |
Maulik V Vaghela | 8d9262a | 2019-12-03 16:12:13 +0530 | [diff] [blame] | 91 | |
| 92 | pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4); |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 93 | |
| 94 | if (pmc_reg_value != 0xffffffff) { |
| 95 | /* Disable Io Space before changing the address */ |
Maulik V Vaghela | 8d9262a | 2019-12-03 16:12:13 +0530 | [diff] [blame] | 96 | pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 97 | ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); |
| 98 | /* Program ABASE in PSF3 PMC space BAR4*/ |
Maulik V Vaghela | 8d9262a | 2019-12-03 16:12:13 +0530 | [diff] [blame] | 99 | pcr_write32(PID_PSF3, pmc_base_reg + PCR_PSFX_TO_SHDW_BAR4, |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 100 | ACPI_BASE_ADDRESS); |
| 101 | /* Enable IO Space */ |
Maulik V Vaghela | 8d9262a | 2019-12-03 16:12:13 +0530 | [diff] [blame] | 102 | pcr_rmw32(PID_PSF3, pmc_base_reg + PCR_PSFX_T0_SHDW_PCIEN, |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 103 | ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); |
| 104 | } |
| 105 | } |
| 106 | |
| 107 | static int pch_check_decode_enable(void) |
| 108 | { |
| 109 | uint32_t dmi_control; |
| 110 | |
| 111 | /* |
| 112 | * This cycle decoding is only allowed to set when |
| 113 | * DMICTL.SRLOCK is 0. |
| 114 | */ |
| 115 | dmi_control = pcr_read32(PID_DMI, PCR_DMI_DMICTL); |
| 116 | if (dmi_control & PCR_DMI_DMICTL_SRLOCK) |
| 117 | return -1; |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | void pch_early_iorange_init(void) |
| 122 | { |
| 123 | uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 | |
| 124 | LPC_IOE_EC_62_66 | LPC_IOE_LGE_200; |
| 125 | |
| 126 | /* IO Decode Range */ |
| 127 | if (CONFIG(DRIVERS_UART_8250IO)) |
| 128 | lpc_io_setup_comm_a_b(); |
| 129 | |
| 130 | /* IO Decode Enable */ |
| 131 | if (pch_check_decode_enable() == 0) { |
| 132 | io_enables = lpc_enable_fixed_io_ranges(io_enables); |
| 133 | /* |
Wim Vervoorn | ee38b99 | 2020-02-03 15:25:49 +0100 | [diff] [blame] | 134 | * Set ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same |
| 135 | * value programmed in ESPI PCI offset 82h. |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 136 | */ |
| 137 | pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); |
Wim Vervoorn | 8440018 | 2020-02-03 15:20:46 +0100 | [diff] [blame] | 138 | /* |
| 139 | * Set LPC IO Decode Ranges PCR[DMI] + 2770h [15:0] to the same |
| 140 | * value programmed in LPC PCI offset 80h. |
| 141 | */ |
| 142 | pcr_write16(PID_DMI, PCR_DMI_LPCIOD, lpc_get_fixed_io_decode()); |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 143 | } |
| 144 | |
| 145 | /* Program generic IO Decode Range */ |
| 146 | pch_enable_lpc(); |
| 147 | } |
| 148 | |
Alexey Buyanov | 1201696 | 2020-07-28 19:59:45 -0700 | [diff] [blame] | 149 | void bootblock_pch_init(void) |
Subrata Banik | 930c31c | 2019-11-01 18:12:58 +0530 | [diff] [blame] | 150 | { |
| 151 | /* |
| 152 | * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT, |
| 153 | * GPE0_STS, GPE0_EN registers. |
| 154 | */ |
| 155 | soc_config_acpibase(); |
| 156 | |
| 157 | /* Set up GPE configuration */ |
| 158 | pmc_gpe_init(); |
| 159 | |
| 160 | enable_rtc_upper_bank(); |
| 161 | } |