- d149bfa soc/intel: Configure P2SB before other PCH controllers by Furquan Shaikh · 3 years, 9 months ago
- 1201696 soc/intel/tigerlake: Rename pch_init() code by Alexey Buyanov · 4 years, 1 month ago
- 45caf97 soc/intel/{cnl,icl,jsl,tgl}: Use Bus Master for setting up PWRMBASE by Subrata Banik · 4 years, 1 month ago
- a1c767a soc/tigerlake: Fix 16-bit read/write PCI_COMMAND register by Elyes HAOUAS · 4 years, 4 months ago
- 6b5bc77 treewide: Remove "this file is part of" lines by Patrick Georgi · 4 years, 3 months ago
- 16f6aa8 soc/intel/tigerlake: Use SPDX for GPL-2.0-only files by Angel Pons · 4 years, 5 months ago
- 555c9b6 soc/intel/tigerlake: Remove Jasper Lake SoC references by Aamir Bohra · 4 years, 5 months ago
- 1c6d8a9 soc: Remove copyright notices by Patrick Georgi · 4 years, 5 months ago
- ee38b99 soc/intel/{cnl,icl,skl,tgl}/bootblock: Update text for DMI PCR 2774 by Wim Vervoorn · 4 years, 7 months ago
- 8440018 soc/intel{cnl,icl,skl,tgl}/bootblock: Make sure DMI PCR 2770 is set by Wim Vervoorn · 4 years, 7 months ago
- 77eaecf soc/intel/tigerlake: Update PMC Register Base and platform check for JSP by Usha P · 4 years, 7 months ago
- 6e33797 soc/intel/tigerlake: Fix PMC config by Ravi Sarawadi · 4 years, 8 months ago
- 5349044 soc/intel/tigerlake: Add required header files in pch.c by Aamir Bohra · 4 years, 8 months ago
- 8d9262a soc/intel/tigerlake: Pick correct pmc base reg from pch type by Maulik V Vaghela · 4 years, 9 months ago
- 5d14c76 soc/intel/{icl,tgl}: Rename pch_early_init() to pch_init() by Subrata Banik · 4 years, 9 months ago
- 930c31c soc/intel/tigerlake/bootblock: Do initial SoC commit till bootblock by Subrata Banik · 4 years, 10 months ago