Blame - src/lib/Kconfig - coreboot

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Nico Huber	4f32b64	2018-10-05 23:40:21 +0200	[diff] [blame]	1	config MISSING_BOARD_RESET
				2	bool
				3	help
				4	Selected by boards that don't provide a do_board_reset()
				5	implementation. This activates a stub that logs the missing
				6	board reset and halts execution.
				7
Jeremy Compostella	fa83887	2022-11-30 19:26:01 -0700	[diff] [blame]	8	config ROMSTAGE_ADA
				9	bool
				10	help
				11	Selected by features that use Ada code in romstage.
				12
Nico Huber	bc652b9	2017-07-17 23:39:02 +0200	[diff] [blame]	13	config RAMSTAGE_ADA
				14	bool
				15	help
				16	Selected by features that use Ada code in ramstage.
				17
				18	config RAMSTAGE_LIBHWBASE
				19	bool
				20	select RAMSTAGE_ADA
				21	help
				22	Selected by features that require `libhwbase` in ramstage.
				23
Jeremy Compostella	50139d0	2022-12-01 15:07:51 -0700	[diff] [blame]	24	config ROMSTAGE_LIBHWBASE
				25	bool
				26	select ROMSTAGE_ADA
				27	help
				28	Selected by features that require `libhwbase` in romstage.
				29
Patrick Rudolph	666c172	2018-04-03 09:57:33 +0200	[diff] [blame]	30	config FLATTENED_DEVICE_TREE
				31	bool
				32	help
				33	Selected by features that require to parse and manipulate a flattened
				34	devicetree in ramstage.
				35
Michael Niewöhner	87cc889	2020-09-07 14:26:09 +0200	[diff] [blame]	36	config HAVE_SPD_IN_CBFS
Elyes HAOUAS	fc46ad8	2019-05-19 11:49:27 +0200	[diff] [blame]	37	bool
				38	help
				39	If enabled, add support for adding spd.hex files in cbfs as spd.bin
Michael Niewöhner	856731d	2020-09-07 13:26:51 +0200	[diff] [blame]	40	and locating it runtime to load SPD.
Elyes HAOUAS	fc46ad8	2019-05-19 11:49:27 +0200	[diff] [blame]	41
				42	config DIMM_MAX
				43	int
				44	default 4
				45	help
				46	Total number of memory DIMM slots available on motherboard.
				47	It is multiplication of number of channel to number of DIMMs per
				48	channel
				49
				50	config DIMM_SPD_SIZE
				51	int
				52	default 256
				53	help
				54	Total SPD size that will be used for DIMM.
				55	Ex: DDR3 256, DDR4 512.
				56
				57	config SPD_READ_BY_WORD
				58	bool
				59
Matt DeVillier	8ead1dc	2020-11-30 14:30:15 -0600	[diff] [blame]	60	config SPD_CACHE_IN_FMAP
				61	bool
				62	default n
				63	help
				64	Enables capability to cache DIMM SPDs in a dedicated FMAP region
				65	to speed loading of SPD data. Currently requires board-level
				66	romstage implementation to read/write/utilize cached SPD data.
				67	When the default FMAP is used, will create a region named RW_SPD_CACHE
				68	to store the cached SPD data.
				69
				70	config SPD_CACHE_FMAP_NAME
				71	string
				72	depends on SPD_CACHE_IN_FMAP
				73	default "RW_SPD_CACHE"
				74	help
				75	Name of the FMAP region created in the default FMAP to cache SPD data.
				76
Jeremy Compostella	50139d0	2022-12-01 15:07:51 -0700	[diff] [blame]	77	if RAMSTAGE_LIBHWBASE && !ROMSTAGE_LIBHWBASE
Nico Huber	bc652b9	2017-07-17 23:39:02 +0200	[diff] [blame]	78
				79	config HWBASE_DYNAMIC_MMIO
				80	def_bool y
				81
Jeremy Compostella	50139d0	2022-12-01 15:07:51 -0700	[diff] [blame]	82	endif
				83
				84	if ROMSTAGE_LIBHWBASE
				85
				86	config HWBASE_STATIC_MMIO
				87	def_bool y
				88
				89	endif
				90
				91	if RAMSTAGE_LIBHWBASE \|\| ROMSTAGE_LIBHWBASE
				92
Nico Huber	625160f	2017-07-17 23:42:33 +0200	[diff] [blame]	93	config HWBASE_DEFAULT_MMCONF
				94	hex
Shelley Chen	4e9bb33	2021-10-20 15:43:45 -0700	[diff] [blame]	95	default ECAM_MMCONF_BASE_ADDRESS
Nico Huber	625160f	2017-07-17 23:42:33 +0200	[diff] [blame]	96
				97	config HWBASE_DIRECT_PCIDEV
				98	def_bool y
				99
Nico Huber	bc652b9	2017-07-17 23:39:02 +0200	[diff] [blame]	100	endif
Julius Werner	7fc9286	2019-11-18 13:01:06 -0800	[diff] [blame]	101
				102	config NO_FMAP_CACHE
				103	bool
				104	help
				105	If your platform really doesn't want to use an FMAP cache (e.g. due to
				106	space constraints), you can select this to disable warnings and save
				107	a bit more code.
Furquan Shaikh	5cc41f2	2020-05-11 12:11:27 -0700	[diff] [blame]	108
				109	config ESPI_DEBUG
				110	bool
				111	help
				112	This option enables eSPI library helper functions for displaying debug
				113	information.
Julius Werner	1e37c9c	2019-12-11 17:09:39 -0800	[diff] [blame]	114
				115	config NO_CBFS_MCACHE
				116	bool
Julius Werner	1e37c9c	2019-12-11 17:09:39 -0800	[diff] [blame]	117	help
				118	Disables the CBFS metadata cache. This means that your platform does
				119	not need to provide a CBFS_MCACHE section in memlayout and can save
				120	the associated CAR/SRAM size. In that case every single CBFS file
				121	lookup must re-read the same CBFS directory entries from flash to find
				122	the respective file.
Raul E Rangel	67798cf	2021-07-02 17:07:05 -0600	[diff] [blame]	123
Raul E Rangel	6938f35	2021-07-23 16:43:18 -0600	[diff] [blame]	124	config CBFS_CACHE_ALIGN
				125	int
				126	default 8
				127	help
				128	Sets the alignment of the buffers returned by the cbfs_cache.
				129
Raul E Rangel	4cfb862	2021-11-01 13:40:14 -0600	[diff] [blame]	130	config CBFS_PRELOAD
				131	bool
				132	depends on COOP_MULTITASKING
				133	help
				134	When enabled it will be possible to preload CBFS files into the
				135	cbfs_cache. This helps reduce boot time by loading the files
				136	in the background before they are actually required. This feature
				137	depends on the read-only boot_device having a DMA controller to
				138	perform the background transfer.
Zheng Bao	d91f3a4	2022-08-03 17:57:47 +0800	[diff] [blame]	139
				140	config DECOMPRESS_OFAST
				141	bool
				142	depends on COMPILER_GCC
				143	default y
				144	help
				145	Compile the decompressing function in -Ofast instead of standard -Os