blob: 0f184252dc01811dd9dba01a3dcc3fd490a8d073 [file] [log] [blame]
Nico Huber4f32b642018-10-05 23:40:21 +02001config MISSING_BOARD_RESET
2 bool
3 help
4 Selected by boards that don't provide a do_board_reset()
5 implementation. This activates a stub that logs the missing
6 board reset and halts execution.
7
Nico Huberbc652b92017-07-17 23:39:02 +02008config RAMSTAGE_ADA
9 bool
10 help
11 Selected by features that use Ada code in ramstage.
12
13config RAMSTAGE_LIBHWBASE
14 bool
15 select RAMSTAGE_ADA
16 help
17 Selected by features that require `libhwbase` in ramstage.
18
Patrick Rudolph666c1722018-04-03 09:57:33 +020019config FLATTENED_DEVICE_TREE
20 bool
21 help
22 Selected by features that require to parse and manipulate a flattened
23 devicetree in ramstage.
24
Michael Niewöhner87cc8892020-09-07 14:26:09 +020025config HAVE_SPD_IN_CBFS
Elyes HAOUASfc46ad82019-05-19 11:49:27 +020026 bool
27 help
28 If enabled, add support for adding spd.hex files in cbfs as spd.bin
Michael Niewöhner856731d2020-09-07 13:26:51 +020029 and locating it runtime to load SPD.
Elyes HAOUASfc46ad82019-05-19 11:49:27 +020030
31config DIMM_MAX
32 int
33 default 4
34 help
35 Total number of memory DIMM slots available on motherboard.
36 It is multiplication of number of channel to number of DIMMs per
37 channel
38
39config DIMM_SPD_SIZE
40 int
41 default 256
42 help
43 Total SPD size that will be used for DIMM.
44 Ex: DDR3 256, DDR4 512.
45
46config SPD_READ_BY_WORD
47 bool
48
Matt DeVillier8ead1dc2020-11-30 14:30:15 -060049config SPD_CACHE_IN_FMAP
50 bool
51 default n
52 help
53 Enables capability to cache DIMM SPDs in a dedicated FMAP region
54 to speed loading of SPD data. Currently requires board-level
55 romstage implementation to read/write/utilize cached SPD data.
56 When the default FMAP is used, will create a region named RW_SPD_CACHE
57 to store the cached SPD data.
58
59config SPD_CACHE_FMAP_NAME
60 string
61 depends on SPD_CACHE_IN_FMAP
62 default "RW_SPD_CACHE"
63 help
64 Name of the FMAP region created in the default FMAP to cache SPD data.
65
Nico Huberbc652b92017-07-17 23:39:02 +020066if RAMSTAGE_LIBHWBASE
67
68config HWBASE_DYNAMIC_MMIO
69 def_bool y
70
Nico Huber625160f2017-07-17 23:42:33 +020071config HWBASE_DEFAULT_MMCONF
72 hex
Shelley Chen4e9bb332021-10-20 15:43:45 -070073 default ECAM_MMCONF_BASE_ADDRESS
Nico Huber625160f2017-07-17 23:42:33 +020074
75config HWBASE_DIRECT_PCIDEV
76 def_bool y
77
Nico Huberbc652b92017-07-17 23:39:02 +020078endif
Julius Werner7fc92862019-11-18 13:01:06 -080079
80config NO_FMAP_CACHE
81 bool
82 help
83 If your platform really doesn't want to use an FMAP cache (e.g. due to
84 space constraints), you can select this to disable warnings and save
85 a bit more code.
Furquan Shaikh5cc41f22020-05-11 12:11:27 -070086
87config ESPI_DEBUG
88 bool
89 help
90 This option enables eSPI library helper functions for displaying debug
91 information.
Julius Werner1e37c9c2019-12-11 17:09:39 -080092
93config NO_CBFS_MCACHE
94 bool
Julius Werner1e37c9c2019-12-11 17:09:39 -080095 help
96 Disables the CBFS metadata cache. This means that your platform does
97 not need to provide a CBFS_MCACHE section in memlayout and can save
98 the associated CAR/SRAM size. In that case every single CBFS file
99 lookup must re-read the same CBFS directory entries from flash to find
100 the respective file.
Raul E Rangel67798cf2021-07-02 17:07:05 -0600101
Raul E Rangel6938f352021-07-23 16:43:18 -0600102config CBFS_CACHE_ALIGN
103 int
104 default 8
105 help
106 Sets the alignment of the buffers returned by the cbfs_cache.
107
Raul E Rangel4cfb8622021-11-01 13:40:14 -0600108config CBFS_PRELOAD
109 bool
110 depends on COOP_MULTITASKING
111 help
112 When enabled it will be possible to preload CBFS files into the
113 cbfs_cache. This helps reduce boot time by loading the files
114 in the background before they are actually required. This feature
115 depends on the read-only boot_device having a DMA controller to
116 perform the background transfer.
117
Raul E Rangel67798cf2021-07-02 17:07:05 -0600118config PAYLOAD_PRELOAD
119 bool
120 depends on COOP_MULTITASKING
121 help
122 On some systems with SPI DMA controllers, it is possible to preload
123 the payload while ramstage is executing. This can be selected by the
124 SoC to enable payload preloading.
125
126 The SoC needs to define a payload_preload_cache region where the
127 raw payload can be placed.