Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 3 | #include <acpi/acpi.h> |
| 4 | #include <acpi/acpigen.h> |
Raul E Rangel | 6fce9cd | 2021-04-06 15:42:51 -0600 | [diff] [blame] | 5 | #include <amdblocks/acpimmio.h> |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 6 | #include <amdblocks/amd_pci_util.h> |
Raul E Rangel | d1a42b6 | 2022-08-10 15:28:15 -0600 | [diff] [blame] | 7 | #include <amdblocks/psp.h> |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 8 | #include <baseboard/variants.h> |
Kyösti Mälkki | 89a5f0f | 2021-06-15 07:22:22 +0300 | [diff] [blame] | 9 | #include <console/console.h> |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 10 | #include <device/device.h> |
Raul E Rangel | d1a42b6 | 2022-08-10 15:28:15 -0600 | [diff] [blame] | 11 | #include <drivers/i2c/tpm/chip.h> |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 12 | #include <gpio.h> |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 13 | #include <soc/acpi.h> |
Mathew King | ad83023 | 2021-02-23 13:08:15 -0700 | [diff] [blame] | 14 | #include <variant/ec.h> |
Felix Held | ce93405 | 2022-10-25 23:58:06 +0200 | [diff] [blame] | 15 | #include <string.h> |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 16 | |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 17 | #define BACKLIGHT_GPIO GPIO_129 |
Karthikeyan Ramasubramanian | d086e3d | 2021-10-08 17:04:10 -0600 | [diff] [blame] | 18 | #define WWAN_AUX_RST_GPIO GPIO_18 |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 19 | #define METHOD_BACKLIGHT_ENABLE "\\_SB.BKEN" |
| 20 | #define METHOD_BACKLIGHT_DISABLE "\\_SB.BKDS" |
| 21 | #define METHOD_MAINBOARD_INI "\\_SB.MINI" |
| 22 | #define METHOD_MAINBOARD_WAK "\\_SB.MWAK" |
| 23 | #define METHOD_MAINBOARD_PTS "\\_SB.MPTS" |
Karthikeyan Ramasubramanian | d086e3d | 2021-10-08 17:04:10 -0600 | [diff] [blame] | 24 | #define METHOD_MAINBOARD_S0X "\\_SB.MS0X" |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 25 | |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 26 | /* |
| 27 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 28 | * This table is responsible for physically routing the PIC and |
| 29 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 30 | * is read and written via registers 0xC00/0xC01 as an |
| 31 | * Index/Data pair. These values are chipset and mainboard |
| 32 | * dependent and should be updated accordingly. |
| 33 | */ |
Felix Held | bf26485 | 2022-10-25 18:18:36 +0200 | [diff] [blame] | 34 | static uint8_t fch_pic_routing[FCH_IRQ_ROUTING_ENTRIES]; |
| 35 | static uint8_t fch_apic_routing[FCH_IRQ_ROUTING_ENTRIES]; |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 36 | |
| 37 | /* |
| 38 | * This controls the device -> IRQ routing. |
| 39 | * |
| 40 | * Hardcoded IRQs: |
| 41 | * 0: timer < soc/amd/common/acpi/lpc.asl |
| 42 | * 1: i8042 - Keyboard |
| 43 | * 2: cascade |
| 44 | * 8: rtc0 <- soc/amd/common/acpi/lpc.asl |
| 45 | * 9: acpi <- soc/amd/common/acpi/lpc.asl |
| 46 | */ |
Felix Held | 067f703 | 2022-10-25 23:30:43 +0200 | [diff] [blame] | 47 | static const struct fch_irq_routing fch_irq_map[] = { |
Raul E Rangel | 6d9a0ea | 2021-05-04 14:29:09 -0600 | [diff] [blame] | 48 | { PIRQ_A, 12, PIRQ_NC }, |
| 49 | { PIRQ_B, 14, PIRQ_NC }, |
| 50 | { PIRQ_C, 15, PIRQ_NC }, |
| 51 | { PIRQ_D, 12, PIRQ_NC }, |
| 52 | { PIRQ_E, 14, PIRQ_NC }, |
| 53 | { PIRQ_F, 15, PIRQ_NC }, |
| 54 | { PIRQ_G, 12, PIRQ_NC }, |
| 55 | { PIRQ_H, 14, PIRQ_NC }, |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 56 | |
| 57 | { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, |
| 58 | { PIRQ_SD, PIRQ_NC, PIRQ_NC }, |
| 59 | { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, |
| 60 | { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, |
| 61 | { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, |
Raul E Rangel | cce7d82 | 2021-03-30 15:50:43 -0600 | [diff] [blame] | 62 | { PIRQ_GPIO, 11, 11 }, |
| 63 | { PIRQ_I2C0, 10, 10 }, |
| 64 | { PIRQ_I2C1, 7, 7 }, |
| 65 | { PIRQ_I2C2, 6, 6 }, |
| 66 | { PIRQ_I2C3, 5, 5 }, |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 67 | { PIRQ_UART0, 4, 4 }, |
| 68 | { PIRQ_UART1, 3, 3 }, |
| 69 | |
| 70 | /* The MISC registers are not interrupt numbers */ |
| 71 | { PIRQ_MISC, 0xfa, 0x00 }, |
| 72 | { PIRQ_MISC0, 0x91, 0x00 }, |
| 73 | { PIRQ_HPET_L, 0x00, 0x00 }, |
| 74 | { PIRQ_HPET_H, 0x00, 0x00 }, |
| 75 | }; |
| 76 | |
Felix Held | df14a02 | 2022-10-25 23:42:15 +0200 | [diff] [blame] | 77 | static const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length) |
| 78 | { |
| 79 | *length = ARRAY_SIZE(fch_irq_map); |
| 80 | return fch_irq_map; |
| 81 | } |
| 82 | |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 83 | static void init_tables(void) |
| 84 | { |
Felix Held | df14a02 | 2022-10-25 23:42:15 +0200 | [diff] [blame] | 85 | const struct fch_irq_routing *mb_irq_map; |
| 86 | size_t mb_fch_irq_mapping_table_size; |
| 87 | size_t i; |
| 88 | |
| 89 | mb_irq_map = mb_get_fch_irq_mapping(&mb_fch_irq_mapping_table_size); |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 90 | |
| 91 | memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); |
| 92 | memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); |
| 93 | |
Felix Held | df14a02 | 2022-10-25 23:42:15 +0200 | [diff] [blame] | 94 | for (i = 0; i < mb_fch_irq_mapping_table_size; i++) { |
| 95 | if (mb_irq_map[i].intr_index >= FCH_IRQ_ROUTING_ENTRIES) { |
| 96 | printk(BIOS_WARNING, |
| 97 | "Invalid IRQ index %u in FCH IRQ routing table entry %zu\n", |
| 98 | mb_irq_map[i].intr_index, i); |
| 99 | continue; |
| 100 | } |
| 101 | fch_pic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].pic_irq_num; |
| 102 | fch_apic_routing[mb_irq_map[i].intr_index] = mb_irq_map[i].apic_irq_num; |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 103 | } |
| 104 | } |
| 105 | |
| 106 | static void pirq_setup(void) |
| 107 | { |
| 108 | intr_data_ptr = fch_apic_routing; |
| 109 | picr_data_ptr = fch_pic_routing; |
| 110 | } |
| 111 | |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 112 | static void mainboard_configure_gpios(void) |
| 113 | { |
| 114 | size_t base_num_gpios, override_num_gpios; |
| 115 | const struct soc_amd_gpio *base_gpios, *override_gpios; |
| 116 | |
Matt DeVillier | 2f4b31f | 2022-09-23 13:28:05 -0500 | [diff] [blame] | 117 | base_gpios = baseboard_gpio_table(&base_num_gpios); |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 118 | override_gpios = variant_override_gpio_table(&override_num_gpios); |
| 119 | |
| 120 | gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, |
| 121 | override_num_gpios); |
| 122 | } |
| 123 | |
Karthikeyan Ramasubramanian | b418298 | 2021-10-26 16:55:35 -0600 | [diff] [blame] | 124 | void __weak variant_devtree_update(void) |
| 125 | { |
| 126 | } |
| 127 | |
Raul E Rangel | d1a42b6 | 2022-08-10 15:28:15 -0600 | [diff] [blame] | 128 | static void configure_psp_tpm_gpio(void) |
| 129 | { |
| 130 | const struct device *cr50_dev = DEV_PTR(cr50); |
| 131 | struct drivers_i2c_tpm_config *cfg = config_of(cr50_dev); |
| 132 | |
| 133 | psp_set_tpm_irq_gpio(cfg->irq_gpio.pins[0]); |
| 134 | } |
| 135 | |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 136 | static void mainboard_init(void *chip_info) |
| 137 | { |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 138 | mainboard_configure_gpios(); |
Mathew King | ad83023 | 2021-02-23 13:08:15 -0700 | [diff] [blame] | 139 | mainboard_ec_init(); |
Karthikeyan Ramasubramanian | b418298 | 2021-10-26 16:55:35 -0600 | [diff] [blame] | 140 | variant_devtree_update(); |
Raul E Rangel | d1a42b6 | 2022-08-10 15:28:15 -0600 | [diff] [blame] | 141 | |
| 142 | /* Run this after variant_devtree_update so the IRQ is correct. */ |
| 143 | configure_psp_tpm_gpio(); |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 144 | } |
| 145 | |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 146 | static void mainboard_write_blken(void) |
| 147 | { |
| 148 | acpigen_write_method(METHOD_BACKLIGHT_ENABLE, 0); |
| 149 | acpigen_soc_clear_tx_gpio(BACKLIGHT_GPIO); |
| 150 | acpigen_pop_len(); |
| 151 | } |
| 152 | |
| 153 | static void mainboard_write_blkdis(void) |
| 154 | { |
| 155 | acpigen_write_method(METHOD_BACKLIGHT_DISABLE, 0); |
| 156 | acpigen_soc_set_tx_gpio(BACKLIGHT_GPIO); |
| 157 | acpigen_pop_len(); |
| 158 | } |
| 159 | |
| 160 | static void mainboard_write_mini(void) |
| 161 | { |
| 162 | acpigen_write_method(METHOD_MAINBOARD_INI, 0); |
| 163 | acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); |
| 164 | acpigen_pop_len(); |
| 165 | } |
| 166 | |
| 167 | static void mainboard_write_mwak(void) |
| 168 | { |
| 169 | acpigen_write_method(METHOD_MAINBOARD_WAK, 0); |
| 170 | acpigen_emit_namestring(METHOD_BACKLIGHT_ENABLE); |
| 171 | acpigen_pop_len(); |
| 172 | } |
| 173 | |
| 174 | static void mainboard_write_mpts(void) |
| 175 | { |
| 176 | acpigen_write_method(METHOD_MAINBOARD_PTS, 0); |
| 177 | acpigen_emit_namestring(METHOD_BACKLIGHT_DISABLE); |
| 178 | acpigen_pop_len(); |
| 179 | } |
| 180 | |
Karthikeyan Ramasubramanian | d086e3d | 2021-10-08 17:04:10 -0600 | [diff] [blame] | 181 | static void mainboard_assert_wwan_aux_reset(void) |
| 182 | { |
| 183 | if (variant_has_pcie_wwan()) |
| 184 | acpigen_soc_clear_tx_gpio(WWAN_AUX_RST_GPIO); |
| 185 | } |
| 186 | |
| 187 | static void mainboard_deassert_wwan_aux_reset(void) |
| 188 | { |
| 189 | if (variant_has_pcie_wwan()) |
| 190 | acpigen_soc_set_tx_gpio(WWAN_AUX_RST_GPIO); |
| 191 | } |
| 192 | |
| 193 | static void mainboard_write_ms0x(void) |
| 194 | { |
| 195 | acpigen_write_method_serialized(METHOD_MAINBOARD_S0X, 1); |
| 196 | /* S0ix Entry */ |
| 197 | acpigen_write_if_lequal_op_int(ARG0_OP, 1); |
| 198 | mainboard_assert_wwan_aux_reset(); |
| 199 | /* S0ix Exit */ |
| 200 | acpigen_write_else(); |
| 201 | mainboard_deassert_wwan_aux_reset(); |
| 202 | acpigen_pop_len(); |
| 203 | acpigen_pop_len(); |
| 204 | } |
| 205 | |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 206 | static void mainboard_fill_ssdt(const struct device *dev) |
| 207 | { |
| 208 | mainboard_write_blken(); |
| 209 | mainboard_write_blkdis(); |
| 210 | mainboard_write_mini(); |
| 211 | mainboard_write_mpts(); |
| 212 | mainboard_write_mwak(); |
Karthikeyan Ramasubramanian | d086e3d | 2021-10-08 17:04:10 -0600 | [diff] [blame] | 213 | mainboard_write_ms0x(); |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 214 | } |
| 215 | |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 216 | static void mainboard_enable(struct device *dev) |
| 217 | { |
Mathew King | 5d47887 | 2021-02-16 14:05:15 -0700 | [diff] [blame] | 218 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 219 | |
Martin Roth | c7204b5 | 2021-03-31 19:15:33 -0600 | [diff] [blame] | 220 | dev->ops->acpi_fill_ssdt = mainboard_fill_ssdt; |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 221 | |
| 222 | init_tables(); |
| 223 | /* Initialize the PIRQ data structures for consumption */ |
| 224 | pirq_setup(); |
Raul E Rangel | 6fce9cd | 2021-04-06 15:42:51 -0600 | [diff] [blame] | 225 | |
| 226 | /* TODO: b/184678786 - Move into espi_config */ |
| 227 | /* Unmask eSPI IRQ 1 (Keyboard) */ |
| 228 | pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | struct chip_operations mainboard_ops = { |
| 232 | .init = mainboard_init, |
| 233 | .enable_dev = mainboard_enable, |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 234 | }; |