Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Raul E Rangel | 6fce9cd | 2021-04-06 15:42:51 -0600 | [diff] [blame^] | 3 | #include <amdblocks/acpimmio.h> |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 4 | #include <amdblocks/amd_pci_util.h> |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 5 | #include <baseboard/variants.h> |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 6 | #include <device/device.h> |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 7 | #include <soc/acpi.h> |
Mathew King | ad83023 | 2021-02-23 13:08:15 -0700 | [diff] [blame] | 8 | #include <variant/ec.h> |
Mathew King | 5d47887 | 2021-02-16 14:05:15 -0700 | [diff] [blame] | 9 | #include <vendorcode/google/chromeos/chromeos.h> |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 10 | |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 11 | /* |
| 12 | * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. |
| 13 | * This table is responsible for physically routing the PIC and |
| 14 | * IOAPIC IRQs to the different PCI devices on the system. It |
| 15 | * is read and written via registers 0xC00/0xC01 as an |
| 16 | * Index/Data pair. These values are chipset and mainboard |
| 17 | * dependent and should be updated accordingly. |
| 18 | */ |
| 19 | static uint8_t fch_pic_routing[0x80]; |
| 20 | static uint8_t fch_apic_routing[0x80]; |
| 21 | |
| 22 | _Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), |
| 23 | "PIC and APIC FCH interrupt tables must be the same size"); |
| 24 | |
| 25 | /* |
| 26 | * This controls the device -> IRQ routing. |
| 27 | * |
| 28 | * Hardcoded IRQs: |
| 29 | * 0: timer < soc/amd/common/acpi/lpc.asl |
| 30 | * 1: i8042 - Keyboard |
| 31 | * 2: cascade |
| 32 | * 8: rtc0 <- soc/amd/common/acpi/lpc.asl |
| 33 | * 9: acpi <- soc/amd/common/acpi/lpc.asl |
| 34 | */ |
| 35 | static const struct fch_irq_routing { |
| 36 | uint8_t intr_index; |
| 37 | uint8_t pic_irq_num; |
| 38 | uint8_t apic_irq_num; |
| 39 | } guybrush_fch[] = { |
| 40 | { PIRQ_A, PIRQ_NC, PIRQ_NC }, |
| 41 | { PIRQ_B, PIRQ_NC, PIRQ_NC }, |
| 42 | { PIRQ_C, PIRQ_NC, PIRQ_NC }, |
| 43 | { PIRQ_D, PIRQ_NC, PIRQ_NC }, |
| 44 | { PIRQ_E, PIRQ_NC, PIRQ_NC }, |
| 45 | { PIRQ_F, PIRQ_NC, PIRQ_NC }, |
| 46 | { PIRQ_G, PIRQ_NC, PIRQ_NC }, |
| 47 | { PIRQ_H, PIRQ_NC, PIRQ_NC }, |
| 48 | |
| 49 | { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ }, |
| 50 | { PIRQ_SD, PIRQ_NC, PIRQ_NC }, |
| 51 | { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, |
| 52 | { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, |
| 53 | { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, |
Raul E Rangel | cce7d82 | 2021-03-30 15:50:43 -0600 | [diff] [blame] | 54 | { PIRQ_GPIO, 11, 11 }, |
| 55 | { PIRQ_I2C0, 10, 10 }, |
| 56 | { PIRQ_I2C1, 7, 7 }, |
| 57 | { PIRQ_I2C2, 6, 6 }, |
| 58 | { PIRQ_I2C3, 5, 5 }, |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 59 | { PIRQ_UART0, 4, 4 }, |
| 60 | { PIRQ_UART1, 3, 3 }, |
| 61 | |
| 62 | /* The MISC registers are not interrupt numbers */ |
| 63 | { PIRQ_MISC, 0xfa, 0x00 }, |
| 64 | { PIRQ_MISC0, 0x91, 0x00 }, |
| 65 | { PIRQ_HPET_L, 0x00, 0x00 }, |
| 66 | { PIRQ_HPET_H, 0x00, 0x00 }, |
| 67 | }; |
| 68 | |
| 69 | static void init_tables(void) |
| 70 | { |
| 71 | const struct fch_irq_routing *entry; |
| 72 | int i; |
| 73 | |
| 74 | memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); |
| 75 | memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); |
| 76 | |
| 77 | for (i = 0; i < ARRAY_SIZE(guybrush_fch); i++) { |
| 78 | entry = guybrush_fch + i; |
| 79 | fch_pic_routing[entry->intr_index] = entry->pic_irq_num; |
| 80 | fch_apic_routing[entry->intr_index] = entry->apic_irq_num; |
| 81 | } |
| 82 | } |
| 83 | |
| 84 | static void pirq_setup(void) |
| 85 | { |
| 86 | intr_data_ptr = fch_apic_routing; |
| 87 | picr_data_ptr = fch_pic_routing; |
| 88 | } |
| 89 | |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 90 | static void mainboard_configure_gpios(void) |
| 91 | { |
| 92 | size_t base_num_gpios, override_num_gpios; |
| 93 | const struct soc_amd_gpio *base_gpios, *override_gpios; |
| 94 | |
| 95 | base_gpios = variant_base_gpio_table(&base_num_gpios); |
| 96 | override_gpios = variant_override_gpio_table(&override_num_gpios); |
| 97 | |
| 98 | gpio_configure_pads_with_override(base_gpios, base_num_gpios, override_gpios, |
| 99 | override_num_gpios); |
| 100 | } |
| 101 | |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 102 | static void mainboard_init(void *chip_info) |
| 103 | { |
Mathew King | 10dd775 | 2021-01-26 16:08:14 -0700 | [diff] [blame] | 104 | mainboard_configure_gpios(); |
Mathew King | ad83023 | 2021-02-23 13:08:15 -0700 | [diff] [blame] | 105 | mainboard_ec_init(); |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | static void mainboard_enable(struct device *dev) |
| 109 | { |
Mathew King | 5d47887 | 2021-02-16 14:05:15 -0700 | [diff] [blame] | 110 | printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); |
| 111 | |
| 112 | dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator; |
Mathew King | 00b490d | 2021-03-12 15:48:32 -0700 | [diff] [blame] | 113 | |
| 114 | init_tables(); |
| 115 | /* Initialize the PIRQ data structures for consumption */ |
| 116 | pirq_setup(); |
Raul E Rangel | 6fce9cd | 2021-04-06 15:42:51 -0600 | [diff] [blame^] | 117 | |
| 118 | /* TODO: b/184678786 - Move into espi_config */ |
| 119 | /* Unmask eSPI IRQ 1 (Keyboard) */ |
| 120 | pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1))); |
Mathew King | 2e2fc7a | 2020-12-08 11:33:58 -0700 | [diff] [blame] | 121 | } |
| 122 | |
| 123 | struct chip_operations mainboard_ops = { |
| 124 | .init = mainboard_init, |
| 125 | .enable_dev = mainboard_enable, |
| 126 | }; |