jinkun.hong | ac490b8 | 2014-06-22 20:40:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2014 Rockchip Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
jinkun.hong | ac490b8 | 2014-06-22 20:40:39 -0700 | [diff] [blame] | 20 | #include <arch/cache.h> |
| 21 | #include <arch/exception.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 22 | #include <arch/stages.h> |
| 23 | #include <armv7.h> |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 24 | #include <assert.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 25 | #include <cbfs.h> |
| 26 | #include <cbmem.h> |
| 27 | #include <console/console.h> |
| 28 | #include <delay.h> |
| 29 | #include <program_loading.h> |
| 30 | #include <soc/sdram.h> |
| 31 | #include <soc/clock.h> |
| 32 | #include <soc/pwm.h> |
| 33 | #include <soc/grf.h> |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 34 | #include <soc/rk808.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 35 | #include <soc/tsadc.h> |
| 36 | #include <stdlib.h> |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 37 | #include <symbols.h> |
Julius Werner | 7a453eb | 2014-10-20 13:14:55 -0700 | [diff] [blame] | 38 | #include <timestamp.h> |
| 39 | #include <types.h> |
| 40 | #include <vendorcode/google/chromeos/chromeos.h> |
| 41 | |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 42 | #include "board.h" |
jinkun.hong | ac490b8 | 2014-06-22 20:40:39 -0700 | [diff] [blame] | 43 | |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 44 | static void regulate_vdd_log(unsigned int mv) |
| 45 | { |
| 46 | unsigned int duty_ns; |
| 47 | const u32 period_ns = 2000; /* pwm period: 2000ns */ |
| 48 | const u32 max_regulator_mv = 1350; /* 1.35V */ |
| 49 | const u32 min_regulator_mv = 870; /* 0.87V */ |
| 50 | |
| 51 | writel(IOMUX_PWM1, &rk3288_grf->iomux_pwm1); |
| 52 | |
| 53 | assert((mv >= min_regulator_mv) && (mv <= max_regulator_mv)); |
| 54 | |
| 55 | duty_ns = (max_regulator_mv - mv) * period_ns / |
| 56 | (max_regulator_mv - min_regulator_mv); |
| 57 | |
| 58 | pwm_init(1, period_ns, duty_ns); |
| 59 | } |
| 60 | |
huang lin | 2d3d452 | 2014-10-16 09:27:31 -0700 | [diff] [blame] | 61 | static void configure_l2ctlr(void) |
| 62 | { |
| 63 | uint32_t l2ctlr; |
| 64 | |
| 65 | l2ctlr = read_l2ctlr(); |
| 66 | l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ |
| 67 | |
| 68 | /* |
| 69 | * Data RAM write latency: 2 cycles |
| 70 | * Data RAM read latency: 2 cycles |
| 71 | * Data RAM setup latency: 1 cycle |
| 72 | * Tag RAM write latency: 1 cycle |
| 73 | * Tag RAM read latency: 1 cycle |
| 74 | * Tag RAM setup latency: 1 cycle |
| 75 | */ |
| 76 | l2ctlr |= (1 << 3 | 1 << 0); |
| 77 | write_l2ctlr(l2ctlr); |
| 78 | } |
| 79 | |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 80 | static void sdmmc_power_off(void) |
| 81 | { |
| 82 | switch (board_id()) { |
| 83 | case 0: |
| 84 | rk808_configure_ldo(PMIC_BUS, 8, 0); /* VCCIO_SD */ |
| 85 | gpio_output(GPIO(7, C, 5), 0); /* SD_EN */ |
| 86 | break; |
| 87 | default: |
| 88 | rk808_configure_ldo(PMIC_BUS, 4, 0); /* VCCIO_SD */ |
| 89 | rk808_configure_ldo(PMIC_BUS, 5, 0); /* VCC33_SD */ |
| 90 | break; |
| 91 | } |
| 92 | } |
| 93 | |
jinkun.hong | ac490b8 | 2014-06-22 20:40:39 -0700 | [diff] [blame] | 94 | void main(void) |
| 95 | { |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame] | 96 | #if CONFIG_COLLECT_TIMESTAMPS |
| 97 | uint64_t start_romstage_time; |
| 98 | uint64_t before_dram_time; |
| 99 | uint64_t after_dram_time; |
| 100 | uint64_t base_time = timestamp_get(); |
| 101 | start_romstage_time = timestamp_get(); |
| 102 | #endif |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame] | 103 | |
| 104 | console_init(); |
huang lin | 2d3d452 | 2014-10-16 09:27:31 -0700 | [diff] [blame] | 105 | configure_l2ctlr(); |
huang lin | a97bd5a | 2014-10-14 10:04:16 -0700 | [diff] [blame] | 106 | tsadc_init(); |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame] | 107 | |
Julius Werner | dbfa9d5 | 2014-12-05 17:29:42 -0800 | [diff] [blame] | 108 | /* Need to power cycle SD card to ensure it is properly reset. */ |
| 109 | sdmmc_power_off(); |
| 110 | |
huang lin | bfdd732 | 2014-09-25 16:33:38 +0800 | [diff] [blame] | 111 | /* vdd_log 1200mv is enough for ddr run 666Mhz */ |
| 112 | regulate_vdd_log(1200); |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame] | 113 | #if CONFIG_COLLECT_TIMESTAMPS |
| 114 | before_dram_time = timestamp_get(); |
| 115 | #endif |
Jinkun Hong | c33ce35 | 2014-08-28 09:37:22 -0700 | [diff] [blame] | 116 | sdram_init(get_sdram_config()); |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame] | 117 | #if CONFIG_COLLECT_TIMESTAMPS |
| 118 | after_dram_time = timestamp_get(); |
| 119 | #endif |
Julius Werner | dae15a6 | 2014-10-15 18:50:45 -0700 | [diff] [blame] | 120 | |
| 121 | /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ |
| 122 | mmu_config_range((uintptr_t)_dram/MiB, |
| 123 | CONFIG_DRAM_SIZE_MB, DCACHE_WRITEBACK); |
Julius Werner | ec5e5e0 | 2014-08-20 15:29:56 -0700 | [diff] [blame] | 124 | mmu_config_range((uintptr_t)_dma_coherent/MiB, |
| 125 | _dma_coherent_size/MiB, DCACHE_OFF); |
jinkun.hong | ac490b8 | 2014-06-22 20:40:39 -0700 | [diff] [blame] | 126 | |
| 127 | cbmem_initialize_empty(); |
| 128 | |
huang lin | 739df1b | 2014-08-27 17:07:42 +0800 | [diff] [blame] | 129 | #if CONFIG_COLLECT_TIMESTAMPS |
| 130 | timestamp_init(base_time); |
| 131 | timestamp_add(TS_START_ROMSTAGE, start_romstage_time); |
| 132 | timestamp_add(TS_BEFORE_INITRAM, before_dram_time); |
| 133 | timestamp_add(TS_AFTER_INITRAM, after_dram_time); |
| 134 | timestamp_add_now(TS_END_ROMSTAGE); |
| 135 | #endif |
Daisuke Nojiri | 5c2988c | 2014-09-24 09:39:16 -0700 | [diff] [blame] | 136 | |
| 137 | #if IS_ENABLED(CONFIG_VBOOT_VERIFY_FIRMWARE) |
Daisuke Nojiri | 742fc8d | 2014-10-10 10:51:06 -0700 | [diff] [blame] | 138 | void *entry = vboot2_load_ramstage(); |
Daisuke Nojiri | 5c2988c | 2014-09-24 09:39:16 -0700 | [diff] [blame] | 139 | if (entry != NULL) |
| 140 | stage_exit(entry); |
| 141 | #endif |
| 142 | |
Aaron Durbin | e4f3e7a | 2015-03-17 13:25:19 -0500 | [diff] [blame] | 143 | run_ramstage(); |
jinkun.hong | ac490b8 | 2014-06-22 20:40:39 -0700 | [diff] [blame] | 144 | } |