Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 - 2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * Copyright (C) 2014 - 2017 Intel Corporation. |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 7 | * Copyright (C) 2018 Online SAS |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; version 2 of the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | */ |
| 19 | |
| 20 | #include <arch/acpi.h> |
| 21 | #include <arch/acpigen.h> |
Elyes HAOUAS | d2b9ec1 | 2018-10-27 09:41:02 +0200 | [diff] [blame] | 22 | #include <arch/cpu.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 23 | #include <arch/smp/mpspec.h> |
| 24 | #include <cpu/x86/smm.h> |
| 25 | #include <string.h> |
| 26 | #include <device/pci.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 27 | #include <cbmem.h> |
| 28 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 29 | #include <intelblocks/acpi.h> |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 30 | #include <soc/acpi.h> |
| 31 | #include <soc/cpu.h> |
| 32 | #include <soc/soc_util.h> |
| 33 | #include <soc/pmc.h> |
| 34 | #include <soc/systemagent.h> |
| 35 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 36 | #define MWAIT_RES(state, sub_state) \ |
| 37 | { \ |
| 38 | .addrl = (((state) << 4) | (sub_state)), \ |
| 39 | .space_id = ACPI_ADDRESS_SPACE_FIXED, \ |
| 40 | .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ |
| 41 | .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ |
| 42 | .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ |
| 43 | } |
| 44 | |
| 45 | #define CSTATE_RES(address_space, width, offset, address) \ |
| 46 | { \ |
| 47 | .space_id = address_space, \ |
| 48 | .bit_width = width, \ |
| 49 | .bit_offset = offset, \ |
| 50 | .addrl = address, \ |
| 51 | } |
| 52 | |
| 53 | static acpi_cstate_t cstate_map[] = { |
| 54 | { |
| 55 | /* C1 */ |
| 56 | .ctype = 1, /* ACPI C1 */ |
| 57 | .latency = 2, |
| 58 | .power = 1000, |
| 59 | .resource = MWAIT_RES(0, 0), |
| 60 | }, |
| 61 | { |
| 62 | .ctype = 2, /* ACPI C2 */ |
| 63 | .latency = 10, |
| 64 | .power = 10, |
| 65 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, |
| 66 | ACPI_BASE_ADDRESS + 0x14), |
| 67 | }, |
| 68 | { |
| 69 | .ctype = 3, /* ACPI C3 */ |
| 70 | .latency = 50, |
| 71 | .power = 10, |
| 72 | .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, |
| 73 | ACPI_BASE_ADDRESS + 0x15), |
| 74 | } |
| 75 | }; |
| 76 | |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 77 | void acpi_init_gnvs(global_nvs_t *gnvs) |
| 78 | { |
| 79 | /* CPU core count */ |
| 80 | gnvs->pcnt = dev_count_cpu(); |
| 81 | |
| 82 | /* Top of Low Memory (start of resource allocation) */ |
| 83 | gnvs->tolm = top_of_32bit_ram(); |
| 84 | |
| 85 | #if IS_ENABLED(CONFIG_CONSOLE_CBMEM) |
| 86 | /* Update the mem console pointer. */ |
| 87 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 88 | #endif |
| 89 | |
| 90 | /* MMIO Low/High & TSEG base and length */ |
| 91 | gnvs->mmiob = (u32)get_top_of_low_memory(); |
| 92 | gnvs->mmiol = (u32)(get_pciebase() - 1); |
| 93 | gnvs->mmiohb = (u64)get_top_of_upper_memory(); |
| 94 | gnvs->mmiohl = (u64)(((u64)1 << CONFIG_CPU_ADDR_BITS) - 1); |
| 95 | gnvs->tsegb = (u32)get_tseg_memory(); |
| 96 | gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory()); |
| 97 | } |
| 98 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 99 | uint32_t soc_read_sci_irq_select(void) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 100 | { |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 101 | struct device *dev = get_pmc_dev(); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 102 | |
| 103 | if (!dev) |
| 104 | return 0; |
| 105 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 106 | return pci_read_config32(dev, PMC_ACPI_CNT); |
| 107 | } |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 108 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 109 | acpi_cstate_t *soc_get_cstate_map(size_t *entries) |
| 110 | { |
| 111 | *entries = ARRAY_SIZE(cstate_map); |
| 112 | return cstate_map; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 113 | } |
| 114 | |
| 115 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 116 | { |
| 117 | u32 pciexbar_reg; |
| 118 | int max_buses; |
| 119 | |
| 120 | pciexbar_reg = get_pciebase(); |
| 121 | max_buses = get_pcielength(); |
| 122 | |
| 123 | if (!pciexbar_reg) |
| 124 | return current; |
| 125 | |
| 126 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 127 | pciexbar_reg, 0x0, 0x0, |
| 128 | (u8)(max_buses - 1)); |
| 129 | |
| 130 | return current; |
| 131 | } |
| 132 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 133 | __attribute__ ((weak)) void motherboard_fill_fadt(acpi_fadt_t *fadt) |
| 134 | { |
| 135 | } |
| 136 | |
| 137 | void soc_fill_fadt(acpi_fadt_t *fadt) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 138 | { |
| 139 | u16 pmbase = get_pmbase(); |
| 140 | |
| 141 | /* System Management */ |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 142 | if (!IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { |
| 143 | fadt->smi_cmd = 0x00; |
| 144 | fadt->acpi_enable = 0x00; |
| 145 | fadt->acpi_disable = 0x00; |
| 146 | } |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 147 | |
| 148 | /* Power Control */ |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 149 | fadt->pm2_cnt_blk = pmbase + PM2_CNT; |
| 150 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 151 | fadt->gpe1_blk = 0; |
| 152 | |
| 153 | /* Control Registers - Length */ |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 154 | fadt->pm2_cnt_len = 1; |
| 155 | fadt->pm_tmr_len = 4; |
| 156 | fadt->gpe0_blk_len = 8; |
| 157 | fadt->gpe1_blk_len = 0; |
| 158 | fadt->gpe1_base = 0; |
| 159 | fadt->cst_cnt = 0; |
| 160 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 161 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 162 | fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 163 | fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 164 | fadt->duty_offset = 1; |
| 165 | fadt->duty_width = 0; |
| 166 | |
| 167 | /* RTC Registers */ |
| 168 | fadt->day_alrm = 0x0D; |
| 169 | fadt->mon_alrm = 0x00; |
| 170 | fadt->century = 0x00; |
| 171 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 172 | |
| 173 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 174 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 175 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | |
| 176 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 177 | |
| 178 | /* Reset Register */ |
| 179 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 180 | fadt->reset_reg.bit_width = 8; |
| 181 | fadt->reset_reg.bit_offset = 0; |
| 182 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 183 | fadt->reset_reg.addrl = 0xCF9; |
| 184 | fadt->reset_reg.addrh = 0x00; |
| 185 | fadt->reset_value = 6; |
| 186 | |
| 187 | /* PM1 Status & PM1 Enable */ |
| 188 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 189 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 190 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 191 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 192 | fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; |
| 193 | fadt->x_pm1a_evt_blk.addrh = 0x00; |
| 194 | |
| 195 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 196 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 197 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 198 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 199 | fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; |
| 200 | fadt->x_pm1b_evt_blk.addrh = 0x00; |
| 201 | |
| 202 | /* PM1 Control Registers */ |
| 203 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 204 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 205 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 206 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 207 | fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; |
| 208 | fadt->x_pm1a_cnt_blk.addrh = 0x00; |
| 209 | |
| 210 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 211 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 212 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 213 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 214 | fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; |
| 215 | fadt->x_pm1b_cnt_blk.addrh = 0x00; |
| 216 | |
| 217 | /* PM2 Control Registers */ |
| 218 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 219 | fadt->x_pm2_cnt_blk.bit_width = 8; |
| 220 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 221 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 222 | fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; |
| 223 | fadt->x_pm2_cnt_blk.addrh = 0x00; |
| 224 | |
| 225 | /* PM1 Timer Register */ |
| 226 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 227 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 228 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 229 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 230 | fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; |
| 231 | fadt->x_pm_tmr_blk.addrh = 0x00; |
| 232 | |
| 233 | /* General-Purpose Event Registers */ |
| 234 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 235 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ |
| 236 | fadt->x_gpe0_blk.bit_offset = 0; |
| 237 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 238 | fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
| 239 | fadt->x_gpe0_blk.addrh = 0x00; |
| 240 | |
| 241 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 242 | fadt->x_gpe1_blk.bit_width = 0; |
| 243 | fadt->x_gpe1_blk.bit_offset = 0; |
| 244 | fadt->x_gpe1_blk.access_size = 0; |
| 245 | fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; |
| 246 | fadt->x_gpe1_blk.addrh = 0x00; |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 247 | |
| 248 | motherboard_fill_fadt(fadt); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 249 | } |
| 250 | |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 251 | int soc_madt_sci_irq_polarity(int sci) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 252 | { |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 253 | if (sci >= 20) |
| 254 | return MP_IRQ_POLARITY_LOW; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 255 | else |
Julien Viard de Galbert | cf2b72f | 2018-04-05 11:24:45 +0200 | [diff] [blame^] | 256 | return MP_IRQ_POLARITY_HIGH; |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 257 | } |
| 258 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 259 | unsigned long southcluster_write_acpi_tables(struct device *device, |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 260 | unsigned long current, |
| 261 | struct acpi_rsdp *rsdp) |
| 262 | { |
| 263 | acpi_header_t *ssdt2; |
| 264 | |
| 265 | current = acpi_write_hpet(device, current, rsdp); |
| 266 | current = (ALIGN(current, 16)); |
| 267 | |
| 268 | ssdt2 = (acpi_header_t *)current; |
| 269 | memset(ssdt2, 0, sizeof(acpi_header_t)); |
| 270 | acpi_create_serialio_ssdt(ssdt2); |
| 271 | if (ssdt2->length) { |
| 272 | current += ssdt2->length; |
| 273 | acpi_add_table(rsdp, ssdt2); |
| 274 | printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, |
| 275 | ssdt2->length); |
| 276 | current = (ALIGN(current, 16)); |
| 277 | } else { |
| 278 | ssdt2 = NULL; |
| 279 | printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); |
| 280 | } |
| 281 | |
| 282 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 283 | |
| 284 | return current; |
| 285 | } |
| 286 | |
Elyes HAOUAS | 2ec4183 | 2018-05-27 17:40:58 +0200 | [diff] [blame] | 287 | void southcluster_inject_dsdt(struct device *device) |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 288 | { |
| 289 | global_nvs_t *gnvs; |
| 290 | |
| 291 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 292 | if (!gnvs) { |
| 293 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
| 294 | if (gnvs) |
| 295 | memset(gnvs, 0, sizeof(*gnvs)); |
| 296 | } |
| 297 | |
| 298 | if (gnvs) { |
| 299 | acpi_create_gnvs(gnvs); |
Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame] | 300 | /* And tell SMI about it */ |
| 301 | smm_setup_structures(gnvs, NULL, NULL); |
| 302 | |
| 303 | /* Add it to DSDT. */ |
| 304 | acpigen_write_scope("\\"); |
| 305 | acpigen_write_name_dword("NVSA", (u32)gnvs); |
| 306 | acpigen_pop_len(); |
| 307 | } |
| 308 | } |
| 309 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 310 | __weak void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} |