Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 - 2009 coresystems GmbH |
| 5 | * Copyright (C) 2013 Google Inc. |
| 6 | * Copyright (C) 2014 - 2017 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | */ |
| 18 | |
| 19 | #include <arch/acpi.h> |
| 20 | #include <arch/acpigen.h> |
| 21 | #include <arch/smp/mpspec.h> |
| 22 | #include <cpu/x86/smm.h> |
| 23 | #include <string.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <cpu/cpu.h> |
| 26 | #include <cbmem.h> |
| 27 | |
| 28 | #include <soc/acpi.h> |
| 29 | #include <soc/cpu.h> |
| 30 | #include <soc/soc_util.h> |
| 31 | #include <soc/pmc.h> |
| 32 | #include <soc/systemagent.h> |
| 33 | |
| 34 | void acpi_init_gnvs(global_nvs_t *gnvs) |
| 35 | { |
| 36 | /* CPU core count */ |
| 37 | gnvs->pcnt = dev_count_cpu(); |
| 38 | |
| 39 | /* Top of Low Memory (start of resource allocation) */ |
| 40 | gnvs->tolm = top_of_32bit_ram(); |
| 41 | |
| 42 | #if IS_ENABLED(CONFIG_CONSOLE_CBMEM) |
| 43 | /* Update the mem console pointer. */ |
| 44 | gnvs->cbmc = (u32)cbmem_find(CBMEM_ID_CONSOLE); |
| 45 | #endif |
| 46 | |
| 47 | /* MMIO Low/High & TSEG base and length */ |
| 48 | gnvs->mmiob = (u32)get_top_of_low_memory(); |
| 49 | gnvs->mmiol = (u32)(get_pciebase() - 1); |
| 50 | gnvs->mmiohb = (u64)get_top_of_upper_memory(); |
| 51 | gnvs->mmiohl = (u64)(((u64)1 << CONFIG_CPU_ADDR_BITS) - 1); |
| 52 | gnvs->tsegb = (u32)get_tseg_memory(); |
| 53 | gnvs->tsegl = (u32)(get_top_of_low_memory() - get_tseg_memory()); |
| 54 | } |
| 55 | |
| 56 | static int acpi_sci_irq(void) |
| 57 | { |
| 58 | int scis, sci_irq; |
| 59 | device_t dev = get_pmc_dev(); |
| 60 | |
| 61 | if (!dev) |
| 62 | return 0; |
| 63 | |
| 64 | /* Determine how SCI is routed. */ |
| 65 | scis = pci_read_config32(dev, PMC_ACPI_CNT) & PMC_ACPI_CNT_SCIS_MASK; |
| 66 | switch (scis) { |
| 67 | case PMC_ACPI_CNT_SCIS_IRQ9: |
| 68 | case PMC_ACPI_CNT_SCIS_IRQ10: |
| 69 | case PMC_ACPI_CNT_SCIS_IRQ11: |
| 70 | sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ9 + 9; |
| 71 | break; |
| 72 | case PMC_ACPI_CNT_SCIS_IRQ20: |
| 73 | case PMC_ACPI_CNT_SCIS_IRQ21: |
| 74 | case PMC_ACPI_CNT_SCIS_IRQ22: |
| 75 | case PMC_ACPI_CNT_SCIS_IRQ23: |
| 76 | sci_irq = scis - PMC_ACPI_CNT_SCIS_IRQ20 + 20; |
| 77 | break; |
| 78 | default: |
| 79 | printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); |
| 80 | sci_irq = 9; |
| 81 | break; |
| 82 | } |
| 83 | |
| 84 | printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); |
| 85 | return sci_irq; |
| 86 | } |
| 87 | |
| 88 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 89 | { |
| 90 | u32 pciexbar_reg; |
| 91 | int max_buses; |
| 92 | |
| 93 | pciexbar_reg = get_pciebase(); |
| 94 | max_buses = get_pcielength(); |
| 95 | |
| 96 | if (!pciexbar_reg) |
| 97 | return current; |
| 98 | |
| 99 | current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, |
| 100 | pciexbar_reg, 0x0, 0x0, |
| 101 | (u8)(max_buses - 1)); |
| 102 | |
| 103 | return current; |
| 104 | } |
| 105 | |
| 106 | void acpi_fill_in_fadt(acpi_fadt_t *fadt) |
| 107 | { |
| 108 | u16 pmbase = get_pmbase(); |
| 109 | |
| 110 | /* System Management */ |
| 111 | fadt->sci_int = acpi_sci_irq(); |
| 112 | #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) |
| 113 | fadt->smi_cmd = APM_CNT; |
| 114 | fadt->acpi_enable = APM_CNT_ACPI_ENABLE; |
| 115 | fadt->acpi_disable = APM_CNT_ACPI_DISABLE; |
| 116 | #else |
| 117 | fadt->smi_cmd = 0x00; |
| 118 | fadt->acpi_enable = 0x00; |
| 119 | fadt->acpi_disable = 0x00; |
| 120 | #endif |
| 121 | |
| 122 | /* Power Control */ |
| 123 | fadt->s4bios_req = 0x0; |
| 124 | fadt->pstate_cnt = 0; |
| 125 | |
| 126 | fadt->pm1a_evt_blk = pmbase + PM1_STS; |
| 127 | fadt->pm1b_evt_blk = 0x0; |
| 128 | fadt->pm1a_cnt_blk = pmbase + PM1_CNT; |
| 129 | fadt->pm1b_cnt_blk = 0x0; |
| 130 | fadt->pm2_cnt_blk = pmbase + PM2_CNT; |
| 131 | fadt->pm_tmr_blk = pmbase + PM1_TMR; |
| 132 | fadt->gpe0_blk = pmbase + GPE0_STS; |
| 133 | fadt->gpe1_blk = 0; |
| 134 | |
| 135 | /* Control Registers - Length */ |
| 136 | fadt->pm1_evt_len = 4; |
| 137 | fadt->pm1_cnt_len = 2; |
| 138 | fadt->pm2_cnt_len = 1; |
| 139 | fadt->pm_tmr_len = 4; |
| 140 | fadt->gpe0_blk_len = 8; |
| 141 | fadt->gpe1_blk_len = 0; |
| 142 | fadt->gpe1_base = 0; |
| 143 | fadt->cst_cnt = 0; |
| 144 | fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; |
| 145 | fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; |
| 146 | fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 147 | fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ |
| 148 | fadt->duty_offset = 1; |
| 149 | fadt->duty_width = 0; |
| 150 | |
| 151 | /* RTC Registers */ |
| 152 | fadt->day_alrm = 0x0D; |
| 153 | fadt->mon_alrm = 0x00; |
| 154 | fadt->century = 0x00; |
| 155 | fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; |
| 156 | |
| 157 | fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | |
| 158 | ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | |
| 159 | ACPI_FADT_RESET_REGISTER | ACPI_FADT_SLEEP_TYPE | |
| 160 | ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; |
| 161 | |
| 162 | /* Reset Register */ |
| 163 | fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; |
| 164 | fadt->reset_reg.bit_width = 8; |
| 165 | fadt->reset_reg.bit_offset = 0; |
| 166 | fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 167 | fadt->reset_reg.addrl = 0xCF9; |
| 168 | fadt->reset_reg.addrh = 0x00; |
| 169 | fadt->reset_value = 6; |
| 170 | |
| 171 | /* PM1 Status & PM1 Enable */ |
| 172 | fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 173 | fadt->x_pm1a_evt_blk.bit_width = 32; |
| 174 | fadt->x_pm1a_evt_blk.bit_offset = 0; |
| 175 | fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 176 | fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk; |
| 177 | fadt->x_pm1a_evt_blk.addrh = 0x00; |
| 178 | |
| 179 | fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 180 | fadt->x_pm1b_evt_blk.bit_width = 0; |
| 181 | fadt->x_pm1b_evt_blk.bit_offset = 0; |
| 182 | fadt->x_pm1b_evt_blk.access_size = 0; |
| 183 | fadt->x_pm1b_evt_blk.addrl = fadt->pm1b_evt_blk; |
| 184 | fadt->x_pm1b_evt_blk.addrh = 0x00; |
| 185 | |
| 186 | /* PM1 Control Registers */ |
| 187 | fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 188 | fadt->x_pm1a_cnt_blk.bit_width = 16; |
| 189 | fadt->x_pm1a_cnt_blk.bit_offset = 0; |
| 190 | fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; |
| 191 | fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; |
| 192 | fadt->x_pm1a_cnt_blk.addrh = 0x00; |
| 193 | |
| 194 | fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 195 | fadt->x_pm1b_cnt_blk.bit_width = 0; |
| 196 | fadt->x_pm1b_cnt_blk.bit_offset = 0; |
| 197 | fadt->x_pm1b_cnt_blk.access_size = 0; |
| 198 | fadt->x_pm1b_cnt_blk.addrl = fadt->pm1b_cnt_blk; |
| 199 | fadt->x_pm1b_cnt_blk.addrh = 0x00; |
| 200 | |
| 201 | /* PM2 Control Registers */ |
| 202 | fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 203 | fadt->x_pm2_cnt_blk.bit_width = 8; |
| 204 | fadt->x_pm2_cnt_blk.bit_offset = 0; |
| 205 | fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; |
| 206 | fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk; |
| 207 | fadt->x_pm2_cnt_blk.addrh = 0x00; |
| 208 | |
| 209 | /* PM1 Timer Register */ |
| 210 | fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 211 | fadt->x_pm_tmr_blk.bit_width = 32; |
| 212 | fadt->x_pm_tmr_blk.bit_offset = 0; |
| 213 | fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 214 | fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; |
| 215 | fadt->x_pm_tmr_blk.addrh = 0x00; |
| 216 | |
| 217 | /* General-Purpose Event Registers */ |
| 218 | fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 219 | fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + EventEnable */ |
| 220 | fadt->x_gpe0_blk.bit_offset = 0; |
| 221 | fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; |
| 222 | fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; |
| 223 | fadt->x_gpe0_blk.addrh = 0x00; |
| 224 | |
| 225 | fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; |
| 226 | fadt->x_gpe1_blk.bit_width = 0; |
| 227 | fadt->x_gpe1_blk.bit_offset = 0; |
| 228 | fadt->x_gpe1_blk.access_size = 0; |
| 229 | fadt->x_gpe1_blk.addrl = fadt->gpe1_blk; |
| 230 | fadt->x_gpe1_blk.addrh = 0x00; |
| 231 | } |
| 232 | |
| 233 | void generate_cpu_entries(device_t device) |
| 234 | { |
| 235 | int core; |
| 236 | int pcontrol_blk = get_pmbase(), plen = 6; |
| 237 | int num_cpus = get_cpu_count(); |
| 238 | |
| 239 | for (core = 0; core < num_cpus; core++) { |
| 240 | if (core > 0) { |
| 241 | pcontrol_blk = 0; |
| 242 | plen = 0; |
| 243 | } |
| 244 | |
| 245 | /* Generate processor \_PR.CPUx */ |
| 246 | acpigen_write_processor(core, pcontrol_blk, plen); |
| 247 | |
| 248 | /* Generate P-state tables */ |
| 249 | |
| 250 | /* Generate C-state tables */ |
| 251 | |
| 252 | /* Generate T-state tables */ |
| 253 | |
| 254 | acpigen_pop_len(); |
| 255 | } |
| 256 | } |
| 257 | |
| 258 | unsigned long acpi_madt_irq_overrides(unsigned long current) |
| 259 | { |
| 260 | int sci_irq = acpi_sci_irq(); |
| 261 | acpi_madt_irqoverride_t *irqovr; |
| 262 | uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; |
| 263 | |
| 264 | /* INT_SRC_OVR */ |
| 265 | irqovr = (acpi_madt_irqoverride_t *)current; |
| 266 | current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); |
| 267 | |
| 268 | if (sci_irq >= 20) |
| 269 | sci_flags |= MP_IRQ_POLARITY_LOW; |
| 270 | else |
| 271 | sci_flags |= MP_IRQ_POLARITY_HIGH; |
| 272 | |
| 273 | irqovr = (acpi_madt_irqoverride_t *)current; |
| 274 | current += acpi_create_madt_irqoverride(irqovr, 0, (u8)sci_irq, sci_irq, |
| 275 | sci_flags); |
| 276 | |
| 277 | return current; |
| 278 | } |
| 279 | |
| 280 | unsigned long southcluster_write_acpi_tables(device_t device, |
| 281 | unsigned long current, |
| 282 | struct acpi_rsdp *rsdp) |
| 283 | { |
| 284 | acpi_header_t *ssdt2; |
| 285 | |
| 286 | current = acpi_write_hpet(device, current, rsdp); |
| 287 | current = (ALIGN(current, 16)); |
| 288 | |
| 289 | ssdt2 = (acpi_header_t *)current; |
| 290 | memset(ssdt2, 0, sizeof(acpi_header_t)); |
| 291 | acpi_create_serialio_ssdt(ssdt2); |
| 292 | if (ssdt2->length) { |
| 293 | current += ssdt2->length; |
| 294 | acpi_add_table(rsdp, ssdt2); |
| 295 | printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, |
| 296 | ssdt2->length); |
| 297 | current = (ALIGN(current, 16)); |
| 298 | } else { |
| 299 | ssdt2 = NULL; |
| 300 | printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n"); |
| 301 | } |
| 302 | |
| 303 | printk(BIOS_DEBUG, "current = %lx\n", current); |
| 304 | |
| 305 | return current; |
| 306 | } |
| 307 | |
| 308 | void southcluster_inject_dsdt(device_t device) |
| 309 | { |
| 310 | global_nvs_t *gnvs; |
| 311 | |
| 312 | gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); |
| 313 | if (!gnvs) { |
| 314 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
| 315 | if (gnvs) |
| 316 | memset(gnvs, 0, sizeof(*gnvs)); |
| 317 | } |
| 318 | |
| 319 | if (gnvs) { |
| 320 | acpi_create_gnvs(gnvs); |
| 321 | acpi_save_gnvs((unsigned long)gnvs); |
| 322 | /* And tell SMI about it */ |
| 323 | smm_setup_structures(gnvs, NULL, NULL); |
| 324 | |
| 325 | /* Add it to DSDT. */ |
| 326 | acpigen_write_scope("\\"); |
| 327 | acpigen_write_name_dword("NVSA", (u32)gnvs); |
| 328 | acpigen_pop_len(); |
| 329 | } |
| 330 | } |
| 331 | |
| 332 | __attribute__((weak)) void acpi_create_serialio_ssdt(acpi_header_t *ssdt) {} |