blob: 3bb042e74f7dae728de85e3ed16097af238c103b [file] [log] [blame]
Uwe Hermannc70e9fc2010-02-15 23:10:19 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Patrick Georgi0588d192009-08-12 15:00:51 +000015
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020016config NORTHBRIDGE_INTEL_I945
Patrick Georgi0588d192009-08-12 15:00:51 +000017 bool
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020018
19if NORTHBRIDGE_INTEL_I945
20
21config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
22 def_bool y
Jens Rottmann0d11f2d2010-08-26 12:46:02 +000023 select HAVE_DEBUG_RAM_SETUP
Denis 'GNUtoo' Cariklifd39ddd2013-06-04 04:48:11 +020024 select LAPIC_MONOTONIC_TIMER
Paul Menzelea8f3b42014-09-21 12:21:36 +020025 select VGA
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010026 select INTEL_GMA_ACPI
Nico Huber561bebf2017-01-19 16:28:18 +010027 select INTEL_GMA_SSC_ALTERNATE_REF
Kyösti Mälkki122e5bc2016-07-22 22:53:19 +030028 select RELOCATABLE_RAMSTAGE
Patrick Rudolph46cf5c22017-04-03 19:09:45 +020029 select INTEL_EDID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000030
Kyösti Mälkkieb5e28f2012-02-24 16:08:18 +020031config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
32 def_bool n
33config NORTHBRIDGE_INTEL_SUBTYPE_I945GM
34 def_bool n
Peter Stugee4bc0f62010-10-01 09:13:18 +000035
Kyösti Mälkki032c23d2013-07-01 11:21:53 +030036config BOOTBLOCK_NORTHBRIDGE_INIT
37 string
38 default "northbridge/intel/i945/bootblock.c"
39
Stefan Reinauerbccbbe62010-12-19 21:20:14 +000040config VGA_BIOS_ID
Uwe Hermann81b3c0a2009-10-30 12:56:59 +000041 string
Arthur Heymansa6b0fc92016-10-16 17:20:35 +020042 default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM
43 default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC
Patrick Georgi77d66832010-10-01 08:02:45 +000044
45config CHANNEL_XOR_RANDOMIZATION
46 bool
47 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000048
Arthur Heymansc5fba2c2017-05-10 11:33:44 +020049config MMCONF_BASE_ADDRESS
50 hex
51 default 0xf0000000
52
Patrick Georgi77d66832010-10-01 08:02:45 +000053config OVERRIDE_CLOCK_DISABLE
54 bool
55 default n
Patrick Georgi77d66832010-10-01 08:02:45 +000056 help
57 Usually system firmware turns off system memory clock
58 signals to unused SO-DIMM slots to reduce EMI and power
59 consumption.
60 However, some boards do not like unused clock signals to
61 be disabled.
62
63config MAXIMUM_SUPPORTED_FREQUENCY
64 int
65 default 0
Patrick Georgi77d66832010-10-01 08:02:45 +000066 help
67 If non-zero, this designates the maximum DDR frequency
68 the board supports, despite what the chipset should be
69 capable of.
Peter Stugee4bc0f62010-10-01 09:13:18 +000070
Peter Stuge751508a2012-01-27 22:17:09 +010071config CHECK_SLFRCS_ON_RESUME
72 def_bool n
73 help
74 On some boards it may be neccessary to hard reset early
75 during resume from S3 if the SLFRCS register indicates that
76 a memory channel is not guaranteed to be in self-refresh.
77 On other boards the check always creates a false positive,
78 effectively making it impossible to resume.
79
Peter Stugee4bc0f62010-10-01 09:13:18 +000080endif