Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 17 | #include <device/pci_ops.h> |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 18 | #include <arch/ioapic.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 19 | #include <arch/acpi.h> |
| 20 | #include <arch/acpigen.h> |
| 21 | #include <cbmem.h> |
| 22 | #include <chip.h> |
| 23 | #include <console/console.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 24 | #include <cpu/amd/mtrr.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 25 | #include <cpu/x86/lapic_def.h> |
Marshall Dawson | f82aa10 | 2017-09-20 18:01:41 -0600 | [diff] [blame] | 26 | #include <cpu/x86/msr.h> |
Elyes HAOUAS | 400ce55 | 2018-10-12 10:54:30 +0200 | [diff] [blame] | 27 | #include <cpu/amd/msr.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 28 | #include <device/device.h> |
| 29 | #include <device/pci.h> |
| 30 | #include <device/pci_ids.h> |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 31 | #include <romstage_handoff.h> |
Richard Spiegel | 0ad74ac | 2017-12-08 16:53:29 -0700 | [diff] [blame] | 32 | #include <amdblocks/agesawrapper.h> |
| 33 | #include <amdblocks/agesawrapper_call.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 34 | #include <agesa_headers.h> |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 35 | #include <soc/cpu.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 36 | #include <soc/northbridge.h> |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 37 | #include <soc/southbridge.h> |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 38 | #include <soc/pci_devs.h> |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 39 | #include <soc/iomap.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 40 | #include <stdint.h> |
| 41 | #include <stdlib.h> |
| 42 | #include <string.h> |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 43 | #include <arch/bert_storage.h> |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 44 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 45 | static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 46 | u32 io_min, u32 io_max) |
| 47 | { |
| 48 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 49 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 50 | /* io range allocation. Limit */ |
| 51 | tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) |
| 52 | | ((io_max & 0xf0) << (12 - 4)); |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 53 | pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 54 | tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); /* base: ISA and VGA ? */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 55 | pci_write_config32(SOC_ADDR_DEV, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 56 | } |
| 57 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 58 | static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, |
| 59 | u32 mmio_min, u32 mmio_max) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 60 | { |
| 61 | u32 tempreg; |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 62 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 63 | /* io range allocation. Limit */ |
| 64 | tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00); |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 65 | pci_write_config32(SOC_ADDR_DEV, reg + 4, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 66 | tempreg = 3 | (nodeid & 0x30) | (mmio_min & 0xffffff00); |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 67 | pci_write_config32(SOC_ADDR_DEV, reg, tempreg); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 68 | } |
| 69 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 70 | static void read_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 71 | { |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 72 | struct resource *res; |
| 73 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 74 | /* |
| 75 | * This MMCONF resource must be reserved in the PCI domain. |
| 76 | * It is not honored by the coreboot resource allocator if it is in |
| 77 | * the CPU_CLUSTER. |
| 78 | */ |
Aaron Durbin | 3173d44 | 2017-11-03 12:14:25 -0600 | [diff] [blame] | 79 | mmconf_resource(dev, MMIO_CONF_BASE); |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 80 | |
| 81 | /* NB IOAPIC2 resource */ |
| 82 | res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ |
| 83 | res->base = IO_APIC2_ADDR; |
| 84 | res->size = 0x00001000; |
| 85 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 86 | } |
| 87 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 88 | static void set_resource(struct device *dev, struct resource *res, u32 nodeid) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 89 | { |
| 90 | resource_t rbase, rend; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 91 | unsigned int reg, link_num; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 92 | char buf[50]; |
| 93 | |
| 94 | /* Make certain the resource has actually been set */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 95 | if (!(res->flags & IORESOURCE_ASSIGNED)) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 96 | return; |
| 97 | |
| 98 | /* If I have already stored this resource don't worry about it */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 99 | if (res->flags & IORESOURCE_STORED) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 100 | return; |
| 101 | |
| 102 | /* Only handle PCI memory and IO resources */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 103 | if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO))) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 104 | return; |
| 105 | |
| 106 | /* Ensure I am actually looking at a resource of function 1 */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 107 | if ((res->index & 0xffff) < 0x1000) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 108 | return; |
| 109 | |
| 110 | /* Get the base address */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 111 | rbase = res->base; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 112 | |
| 113 | /* Get the limit (rounded up) */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 114 | rend = resource_end(res); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 115 | |
| 116 | /* Get the register and link */ |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 117 | reg = res->index & 0xfff; /* 4k */ |
| 118 | link_num = IOINDEX_LINK(res->index); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 119 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 120 | if (res->flags & IORESOURCE_IO) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 121 | set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 122 | else if (res->flags & IORESOURCE_MEM) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 123 | set_mmio_addr_reg(nodeid, link_num, reg, |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 124 | (res->index >> 24), rbase >> 8, rend >> 8); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 125 | |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 126 | res->flags |= IORESOURCE_STORED; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 127 | snprintf(buf, sizeof(buf), " <node %x link %x>", |
| 128 | nodeid, link_num); |
Richard Spiegel | 2b7cd1d | 2018-10-22 14:39:37 -0700 | [diff] [blame] | 129 | report_resource_stored(dev, res, buf); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 130 | } |
| 131 | |
| 132 | /** |
| 133 | * I tried to reuse the resource allocation code in set_resource() |
| 134 | * but it is too difficult to deal with the resource allocation magic. |
| 135 | */ |
| 136 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 137 | static void create_vga_resource(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 138 | { |
| 139 | struct bus *link; |
| 140 | |
| 141 | /* find out which link the VGA card is connected, |
| 142 | * we only deal with the 'first' vga card */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 143 | for (link = dev->link_list ; link ; link = link->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 144 | if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) |
| 145 | break; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 146 | |
| 147 | /* no VGA card installed */ |
| 148 | if (link == NULL) |
| 149 | return; |
| 150 | |
Marshall Dawson | e2697de | 2017-09-06 10:46:36 -0600 | [diff] [blame] | 151 | printk(BIOS_DEBUG, "VGA: %s has VGA device\n", dev_path(dev)); |
Marshall Dawson | 38bded0 | 2017-09-01 09:54:48 -0600 | [diff] [blame] | 152 | /* Route A0000-BFFFF, IO 3B0-3BB 3C0-3DF */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 153 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 154 | } |
| 155 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 156 | static void set_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 157 | { |
| 158 | struct bus *bus; |
| 159 | struct resource *res; |
| 160 | |
| 161 | |
| 162 | /* do we need this? */ |
| 163 | create_vga_resource(dev); |
| 164 | |
| 165 | /* Set each resource we have found */ |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 166 | for (res = dev->resource_list ; res ; res = res->next) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 167 | set_resource(dev, res, 0); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 168 | |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 169 | for (bus = dev->link_list ; bus ; bus = bus->next) |
| 170 | if (bus->children) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 171 | assign_resources(bus); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 172 | } |
| 173 | |
| 174 | static void northbridge_init(struct device *dev) |
| 175 | { |
Marc Jones | d6a8200 | 2018-03-31 22:46:57 -0600 | [diff] [blame] | 176 | setup_ioapic((u8 *)IO_APIC2_ADDR, CONFIG_MAX_CPUS+1); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 177 | } |
| 178 | |
| 179 | static unsigned long acpi_fill_hest(acpi_hest_t *hest) |
| 180 | { |
| 181 | void *addr, *current; |
| 182 | |
| 183 | /* Skip the HEST header. */ |
| 184 | current = (void *)(hest + 1); |
| 185 | |
| 186 | addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); |
| 187 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 188 | current += acpi_create_hest_error_source(hest, current, 0, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 189 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 190 | |
| 191 | addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); |
| 192 | if (addr != NULL) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 193 | current += acpi_create_hest_error_source(hest, current, 1, |
Richard Spiegel | 271b8a5 | 2018-11-06 16:32:28 -0700 | [diff] [blame] | 194 | (void *)((u32)addr + 2), *(uint16_t *)addr - 2); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 195 | |
| 196 | return (unsigned long)current; |
| 197 | } |
| 198 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 199 | static void northbridge_fill_ssdt_generator(struct device *device) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 200 | { |
| 201 | msr_t msr; |
| 202 | char pscope[] = "\\_SB.PCI0"; |
| 203 | |
| 204 | acpigen_write_scope(pscope); |
| 205 | msr = rdmsr(TOP_MEM); |
| 206 | acpigen_write_name_dword("TOM1", msr.lo); |
| 207 | msr = rdmsr(TOP_MEM2); |
| 208 | /* |
| 209 | * Since XP only implements parts of ACPI 2.0, we can't use a qword |
| 210 | * here. |
| 211 | * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt |
| 212 | * slide 22ff. |
| 213 | * Shift value right by 20 bit to make it fit into 32bit, |
| 214 | * giving us 1MB granularity and a limit of almost 4Exabyte of memory. |
| 215 | */ |
| 216 | acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); |
| 217 | acpigen_pop_len(); |
| 218 | } |
| 219 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 220 | static unsigned long agesa_write_acpi_tables(struct device *device, |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 221 | unsigned long current, |
| 222 | acpi_rsdp_t *rsdp) |
| 223 | { |
| 224 | acpi_srat_t *srat; |
| 225 | acpi_slit_t *slit; |
| 226 | acpi_header_t *ssdt; |
| 227 | acpi_header_t *alib; |
| 228 | acpi_header_t *ivrs; |
| 229 | acpi_hest_t *hest; |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 230 | acpi_bert_t *bert; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 231 | |
| 232 | /* HEST */ |
| 233 | current = ALIGN(current, 8); |
| 234 | hest = (acpi_hest_t *)current; |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 235 | acpi_write_hest(hest, acpi_fill_hest); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 236 | acpi_add_table(rsdp, (void *)current); |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 237 | current += hest->header.length; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 238 | |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 239 | /* BERT */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 240 | if (CONFIG(ACPI_BERT) && bert_errors_present()) { |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 241 | /* Skip the table if no errors are present. ACPI driver reports |
| 242 | * a table with a 0-length region: |
| 243 | * BERT: [Firmware Bug]: table invalid. |
| 244 | */ |
| 245 | void *rgn; |
| 246 | size_t size; |
| 247 | bert_errors_region(&rgn, &size); |
| 248 | if (!rgn) { |
| 249 | printk(BIOS_ERR, "Error: Can't find BERT storage area\n"); |
| 250 | } else { |
| 251 | current = ALIGN(current, 8); |
| 252 | bert = (acpi_bert_t *)current; |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 253 | acpi_write_bert(bert, (uintptr_t)rgn, size); |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 254 | acpi_add_table(rsdp, (void *)current); |
Richard Spiegel | 6a9e6cd | 2018-11-30 10:53:40 -0700 | [diff] [blame] | 255 | current += bert->header.length; |
Marshall Dawson | 653f760 | 2018-09-04 13:25:39 -0600 | [diff] [blame] | 256 | } |
| 257 | } |
| 258 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 259 | current = ALIGN(current, 8); |
| 260 | printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); |
| 261 | ivrs = agesawrapper_getlateinitptr(PICK_IVRS); |
| 262 | if (ivrs != NULL) { |
| 263 | memcpy((void *)current, ivrs, ivrs->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 264 | ivrs = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 265 | current += ivrs->length; |
| 266 | acpi_add_table(rsdp, ivrs); |
| 267 | } else { |
| 268 | printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); |
| 269 | } |
| 270 | |
| 271 | /* SRAT */ |
| 272 | current = ALIGN(current, 8); |
| 273 | printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 274 | srat = (acpi_srat_t *)agesawrapper_getlateinitptr(PICK_SRAT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 275 | if (srat != NULL) { |
| 276 | memcpy((void *)current, srat, srat->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 277 | srat = (acpi_srat_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 278 | current += srat->header.length; |
| 279 | acpi_add_table(rsdp, srat); |
| 280 | } else { |
| 281 | printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); |
| 282 | } |
| 283 | |
| 284 | /* SLIT */ |
| 285 | current = ALIGN(current, 8); |
| 286 | printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 287 | slit = (acpi_slit_t *)agesawrapper_getlateinitptr(PICK_SLIT); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 288 | if (slit != NULL) { |
| 289 | memcpy((void *)current, slit, slit->header.length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 290 | slit = (acpi_slit_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 291 | current += slit->header.length; |
| 292 | acpi_add_table(rsdp, slit); |
| 293 | } else { |
| 294 | printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); |
| 295 | } |
| 296 | |
| 297 | /* ALIB */ |
| 298 | current = ALIGN(current, 16); |
| 299 | printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 300 | alib = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_ALIB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 301 | if (alib != NULL) { |
| 302 | memcpy((void *)current, alib, alib->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 303 | alib = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 304 | current += alib->length; |
| 305 | acpi_add_table(rsdp, (void *)alib); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 306 | } else { |
| 307 | printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL." |
| 308 | " Skipping.\n"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 309 | } |
| 310 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 311 | current = ALIGN(current, 16); |
| 312 | printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 313 | ssdt = (acpi_header_t *)agesawrapper_getlateinitptr(PICK_PSTATE); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 314 | if (ssdt != NULL) { |
| 315 | memcpy((void *)current, ssdt, ssdt->length); |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 316 | ssdt = (acpi_header_t *)current; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 317 | current += ssdt->length; |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 318 | } else { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 319 | printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); |
| 320 | } |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 321 | acpi_add_table(rsdp, ssdt); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 322 | |
| 323 | printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); |
| 324 | return current; |
| 325 | } |
| 326 | |
| 327 | static struct device_operations northbridge_operations = { |
| 328 | .read_resources = read_resources, |
| 329 | .set_resources = set_resources, |
| 330 | .enable_resources = pci_dev_enable_resources, |
| 331 | .init = northbridge_init, |
| 332 | .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, |
| 333 | .write_acpi_tables = agesa_write_acpi_tables, |
| 334 | .enable = 0, |
| 335 | .ops_pci = 0, |
| 336 | }; |
| 337 | |
| 338 | static const struct pci_driver family15_northbridge __pci_driver = { |
| 339 | .ops = &northbridge_operations, |
| 340 | .vendor = PCI_VENDOR_ID_AMD, |
| 341 | .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, |
| 342 | }; |
| 343 | |
Marshall Dawson | 154239a | 2017-11-02 09:49:30 -0600 | [diff] [blame] | 344 | /* |
| 345 | * Enable VGA cycles. Set memory ranges of the FCH legacy devices (TPM, HPET, |
| 346 | * BIOS RAM, Watchdog Timer, IOAPIC and ACPI) as non-posted. Set remaining |
| 347 | * MMIO to posted. Route all I/O to the southbridge. |
| 348 | */ |
| 349 | void amd_initcpuio(void) |
| 350 | { |
| 351 | uintptr_t topmem = bsp_topmem(); |
| 352 | uintptr_t base, limit; |
| 353 | |
| 354 | /* Enable legacy video routing: D18F1xF4 VGA Enable */ |
| 355 | pci_write_config32(SOC_ADDR_DEV, D18F1_VGAEN, VGA_ADDR_ENABLE); |
| 356 | |
| 357 | /* Non-posted: range(HPET-LAPIC) or 0xfed00000 through 0xfee00000-1 */ |
| 358 | base = (HPET_BASE_ADDRESS >> 8) | MMIO_WE | MMIO_RE; |
| 359 | limit = (ALIGN_DOWN(LOCAL_APIC_ADDR - 1, 64 * KiB) >> 8) | MMIO_NP; |
| 360 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(0), limit); |
| 361 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(0), base); |
| 362 | |
| 363 | /* Remaining PCI hole posted MMIO: TOM-HPET (TOM through 0xfed00000-1 */ |
| 364 | base = (topmem >> 8) | MMIO_WE | MMIO_RE; |
| 365 | limit = ALIGN_DOWN(HPET_BASE_ADDRESS - 1, 64 * KiB) >> 8; |
| 366 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_LIMIT_LO(1), limit); |
| 367 | pci_write_config32(SOC_ADDR_DEV, NB_MMIO_BASE_LO(1), base); |
| 368 | |
| 369 | /* Route all I/O downstream */ |
| 370 | base = 0 | IO_WE | IO_RE; |
| 371 | limit = ALIGN_DOWN(0xffff, 4 * KiB); |
| 372 | pci_write_config32(SOC_ADDR_DEV, NB_IO_LIMIT(0), limit); |
| 373 | pci_write_config32(SOC_ADDR_DEV, NB_IO_BASE(0), base); |
| 374 | } |
| 375 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 376 | void fam15_finalize(void *chip_info) |
| 377 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 378 | u32 value; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 379 | |
| 380 | /* TODO: move IOAPIC code to dsdt.asl */ |
| 381 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_INDEX, 0); |
| 382 | pci_write_config32(SOC_GNB_DEV, NB_IOAPIC_DATA, 5); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 383 | |
| 384 | /* disable No Snoop */ |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 385 | value = pci_read_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS); |
Richard Spiegel | 3d34ae3 | 2018-04-13 13:20:08 -0700 | [diff] [blame] | 386 | value &= ~HDA_NO_SNOOP_EN; |
Richard Spiegel | 41baf0c | 2018-10-22 13:57:18 -0700 | [diff] [blame] | 387 | pci_write_config32(SOC_HDA0_DEV, HDA_DEV_CTRL_STATUS, value); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 388 | } |
| 389 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 390 | void domain_enable_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 391 | { |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 392 | /* Must be called after PCI enumeration and resource allocation */ |
Marshall Dawson | 8f2a7e0 | 2017-11-01 11:44:48 -0600 | [diff] [blame] | 393 | if (!romstage_handoff_is_resume()) |
Richard Spiegel | 138a1d2 | 2017-12-13 13:26:21 -0700 | [diff] [blame] | 394 | do_agesawrapper(agesawrapper_amdinitmid, "amdinitmid"); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 395 | } |
| 396 | |
Elyes HAOUAS | 777ccd4 | 2018-05-22 10:52:05 +0200 | [diff] [blame] | 397 | void domain_set_resources(struct device *dev) |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 398 | { |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 399 | uint64_t uma_base = get_uma_base(); |
| 400 | uint32_t uma_size = get_uma_size(); |
| 401 | uint32_t mem_useable = (uintptr_t)cbmem_top(); |
| 402 | msr_t tom = rdmsr(TOP_MEM); |
| 403 | msr_t high_tom = rdmsr(TOP_MEM2); |
| 404 | uint64_t high_mem_useable; |
| 405 | int idx = 0x10; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 406 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 407 | /* 0x0 -> 0x9ffff */ |
| 408 | ram_resource(dev, idx++, 0, 0xa0000 / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 409 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 410 | /* 0xa0000 -> 0xbffff: legacy VGA */ |
| 411 | mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB); |
| 412 | |
| 413 | /* 0xc0000 -> 0xfffff: Option ROM */ |
| 414 | reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 415 | |
Marshall Dawson | 29f1b74 | 2017-09-06 14:59:45 -0600 | [diff] [blame] | 416 | /* |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 417 | * 0x100000 (1MiB) -> low top useable RAM |
| 418 | * cbmem_top() accounts for low UMA and TSEG if they are used. |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 419 | */ |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 420 | ram_resource(dev, idx++, (1 * MiB) / KiB, |
| 421 | (mem_useable - (1 * MiB)) / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 422 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 423 | /* Low top useable RAM -> Low top RAM (bottom pci mmio hole) */ |
| 424 | reserved_ram_resource(dev, idx++, mem_useable / KiB, |
| 425 | (tom.lo - mem_useable) / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 426 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 427 | /* If there is memory above 4GiB */ |
| 428 | if (high_tom.hi) { |
| 429 | /* 4GiB -> high top useable */ |
| 430 | if (uma_base >= (4ull * GiB)) |
| 431 | high_mem_useable = uma_base; |
| 432 | else |
| 433 | high_mem_useable = ((uint64_t)high_tom.lo | |
| 434 | ((uint64_t)high_tom.hi << 32)); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 435 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 436 | ram_resource(dev, idx++, (4ull * GiB) / KiB, |
| 437 | ((high_mem_useable - (4ull * GiB)) / KiB)); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 438 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 439 | /* High top useable RAM -> high top RAM */ |
| 440 | if (uma_base >= (4ull * GiB)) { |
| 441 | reserved_ram_resource(dev, idx++, uma_base / KiB, |
| 442 | uma_size / KiB); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 443 | } |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 444 | } |
| 445 | |
Marc Jones | 5fd1d5a | 2018-02-08 15:41:54 -0700 | [diff] [blame] | 446 | assign_resources(dev->link_list); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 447 | } |
| 448 | |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 449 | /********************************************************************* |
| 450 | * Change the vendor / device IDs to match the generic VBIOS header. * |
| 451 | *********************************************************************/ |
| 452 | u32 map_oprom_vendev(u32 vendev) |
| 453 | { |
| 454 | u32 new_vendev; |
| 455 | new_vendev = |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 456 | ((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ? |
| 457 | 0x100298e0 : vendev; |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 458 | |
| 459 | if (vendev != new_vendev) |
Marshall Dawson | 4e101ad | 2017-06-15 12:17:38 -0600 | [diff] [blame] | 460 | printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", |
| 461 | vendev, new_vendev); |
Marc Jones | 1587dc8 | 2017-05-15 18:55:11 -0600 | [diff] [blame] | 462 | |
| 463 | return new_vendev; |
| 464 | } |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 465 | |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 466 | __weak void set_board_env_params(GNB_ENV_CONFIGURATION *params) { } |
| 467 | |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 468 | void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) |
| 469 | { |
Martin Roth | 50f2e4c | 2018-10-29 11:16:53 -0600 | [diff] [blame] | 470 | const struct device *dev = SOC_IOMMU_DEV; |
| 471 | params->IommuSupport = dev && dev->enabled; |
Richard Spiegel | 2e90ee3 | 2018-07-24 12:08:22 -0700 | [diff] [blame] | 472 | set_board_env_params(params); |
Marshall Dawson | 2942db6 | 2017-12-14 10:00:27 -0700 | [diff] [blame] | 473 | } |
| 474 | |
| 475 | void SetNbMidParams(GNB_MID_CONFIGURATION *params) |
| 476 | { |
| 477 | /* 0=Primary and decode all VGA resources, 1=Secondary - decode none */ |
| 478 | params->iGpuVgaMode = 0; |
| 479 | params->GnbIoapicAddress = IO_APIC2_ADDR; |
| 480 | } |