Martin Roth | 5474eb1 | 2018-05-26 19:22:33 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 14 | #include <console/console.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 15 | #include <device/pci_ops.h> |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 16 | #include <stdint.h> |
| 17 | #include <device/device.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <device/pci_ids.h> |
| 20 | #include <stdlib.h> |
| 21 | #include <string.h> |
Corey Osgood | e562f72 | 2008-12-19 03:36:48 +0000 | [diff] [blame] | 22 | #include <cpu/cpu.h> |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 23 | #include "northbridge.h" |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 24 | #include "i440bx.h" |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 25 | |
Elyes HAOUAS | 64d2d10 | 2018-02-09 08:43:01 +0100 | [diff] [blame] | 26 | static void northbridge_init(struct device *dev) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 27 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 28 | printk(BIOS_SPEW, "Northbridge Init\n"); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 29 | } |
| 30 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 31 | static struct device_operations northbridge_operations = { |
| 32 | .read_resources = pci_dev_read_resources, |
| 33 | .set_resources = pci_dev_set_resources, |
| 34 | .enable_resources = pci_dev_enable_resources, |
| 35 | .init = northbridge_init, |
| 36 | .enable = 0, |
| 37 | .ops_pci = 0, |
| 38 | }; |
| 39 | |
Stefan Reinauer | f1cf1f7 | 2007-10-24 09:08:58 +0000 | [diff] [blame] | 40 | static const struct pci_driver northbridge_driver __pci_driver = { |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 41 | .ops = &northbridge_operations, |
| 42 | .vendor = PCI_VENDOR_ID_INTEL, |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 43 | .device = 0x7190, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 44 | }; |
| 45 | |
Elyes HAOUAS | 64d2d10 | 2018-02-09 08:43:01 +0100 | [diff] [blame] | 46 | static void i440bx_domain_set_resources(struct device *dev) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 47 | { |
Elyes HAOUAS | 322fa32 | 2018-05-09 17:49:56 +0200 | [diff] [blame] | 48 | struct device *mc_dev; |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 49 | uint32_t pci_tolm; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 50 | |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 51 | pci_tolm = find_pci_tolm(dev->link_list); |
| 52 | mc_dev = dev->link_list->children; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 53 | if (mc_dev) { |
| 54 | unsigned long tomk, tolmk; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 55 | int idx; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 56 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 57 | /* Figure out which areas are/should be occupied by RAM. The |
| 58 | * value of the highest DRB denotes the end of the physical |
| 59 | * memory (in units of 8MB). |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 60 | */ |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 61 | tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7)); |
Uwe Hermann | f03e4e9 | 2007-05-10 23:59:20 +0000 | [diff] [blame] | 62 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 63 | /* Convert to KB. */ |
| 64 | tomk *= (8 * 1024); |
| 65 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 66 | printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024); |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 67 | |
| 68 | /* Compute the top of low memory. */ |
| 69 | tolmk = pci_tolm / 1024; |
| 70 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 71 | if (tolmk >= tomk) { |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 72 | /* The PCI hole does not overlap the memory. */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 73 | tolmk = tomk; |
| 74 | } |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 75 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 76 | /* Report the memory regions. */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 77 | idx = 10; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 78 | ram_resource(dev, idx++, 0, 640); |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 79 | ram_resource(dev, idx++, 768, tolmk - 768); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 80 | } |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 81 | assign_resources(dev->link_list); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 82 | } |
| 83 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 84 | static struct device_operations pci_domain_ops = { |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 85 | .read_resources = pci_domain_read_resources, |
Myles Watson | 29cc9ed | 2009-07-02 18:56:24 +0000 | [diff] [blame] | 86 | .set_resources = i440bx_domain_set_resources, |
Myles Watson | 7eac445 | 2010-06-17 16:16:56 +0000 | [diff] [blame] | 87 | .enable_resources = NULL, |
| 88 | .init = NULL, |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 89 | .scan_bus = pci_domain_scan_bus, |
| 90 | }; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 91 | |
Elyes HAOUAS | 64d2d10 | 2018-02-09 08:43:01 +0100 | [diff] [blame] | 92 | static void cpu_bus_init(struct device *dev) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 93 | { |
Myles Watson | 894a347 | 2010-06-09 22:41:35 +0000 | [diff] [blame] | 94 | initialize_cpus(dev->link_list); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 95 | } |
| 96 | |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 97 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 98 | .read_resources = DEVICE_NOOP, |
| 99 | .set_resources = DEVICE_NOOP, |
| 100 | .enable_resources = DEVICE_NOOP, |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 101 | .init = cpu_bus_init, |
| 102 | .scan_bus = 0, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 103 | }; |
| 104 | |
| 105 | static void enable_dev(struct device *dev) |
| 106 | { |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 107 | /* Set the operations if it is a special bus type */ |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 108 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 109 | dev->ops = &pci_domain_ops; |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 110 | } |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 111 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
Myles Watson | 032a965 | 2009-05-11 22:24:53 +0000 | [diff] [blame] | 112 | dev->ops = &cpu_bus_ops; |
| 113 | } |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 114 | } |
| 115 | |
| 116 | struct chip_operations northbridge_intel_i440bx_ops = { |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 117 | CHIP_NAME("Intel 82443BX (440BX) Northbridge") |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 118 | .enable_dev = enable_dev, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 119 | }; |