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Richard Smithcb8eab42006-07-24 04:25:47 +00001#include <console/console.h>
2#include <arch/io.h>
3#include <stdint.h>
4#include <device/device.h>
5#include <device/pci.h>
6#include <device/pci_ids.h>
7#include <stdlib.h>
8#include <string.h>
Stefan Reinauerfd611f92013-02-27 23:45:20 +01009#include <cbmem.h>
Corey Osgoode562f722008-12-19 03:36:48 +000010#include <cpu/cpu.h>
11#include <pc80/keyboard.h>
Richard Smithcb8eab42006-07-24 04:25:47 +000012#include "northbridge.h"
Uwe Hermann1a9c8922007-04-01 17:24:03 +000013#include "i440bx.h"
Richard Smithcb8eab42006-07-24 04:25:47 +000014
Elyes HAOUAS64d2d102018-02-09 08:43:01 +010015static void northbridge_init(struct device *dev)
Richard Smithcb8eab42006-07-24 04:25:47 +000016{
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +000017 printk(BIOS_SPEW, "Northbridge Init\n");
Richard Smithcb8eab42006-07-24 04:25:47 +000018}
19
Richard Smithcb8eab42006-07-24 04:25:47 +000020static struct device_operations northbridge_operations = {
21 .read_resources = pci_dev_read_resources,
22 .set_resources = pci_dev_set_resources,
23 .enable_resources = pci_dev_enable_resources,
24 .init = northbridge_init,
25 .enable = 0,
26 .ops_pci = 0,
27};
28
Stefan Reinauerf1cf1f72007-10-24 09:08:58 +000029static const struct pci_driver northbridge_driver __pci_driver = {
Richard Smithcb8eab42006-07-24 04:25:47 +000030 .ops = &northbridge_operations,
31 .vendor = PCI_VENDOR_ID_INTEL,
Myles Watson032a9652009-05-11 22:24:53 +000032 .device = 0x7190,
Richard Smithcb8eab42006-07-24 04:25:47 +000033};
34
Elyes HAOUAS64d2d102018-02-09 08:43:01 +010035static void i440bx_domain_set_resources(struct device *dev)
Richard Smithcb8eab42006-07-24 04:25:47 +000036{
Elyes HAOUAS322fa322018-05-09 17:49:56 +020037 struct device *mc_dev;
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000038 uint32_t pci_tolm;
Richard Smithcb8eab42006-07-24 04:25:47 +000039
Myles Watson894a3472010-06-09 22:41:35 +000040 pci_tolm = find_pci_tolm(dev->link_list);
41 mc_dev = dev->link_list->children;
Richard Smithcb8eab42006-07-24 04:25:47 +000042 if (mc_dev) {
43 unsigned long tomk, tolmk;
Uwe Hermann1a9c8922007-04-01 17:24:03 +000044 int idx;
Richard Smithcb8eab42006-07-24 04:25:47 +000045
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000046 /* Figure out which areas are/should be occupied by RAM. The
47 * value of the highest DRB denotes the end of the physical
48 * memory (in units of 8MB).
Uwe Hermann1a9c8922007-04-01 17:24:03 +000049 */
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000050 tomk = ((unsigned long)pci_read_config8(mc_dev, DRB7));
Uwe Hermannf03e4e92007-05-10 23:59:20 +000051
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000052 /* Convert to KB. */
53 tomk *= (8 * 1024);
54
Stefan Reinauerc02b4fc2010-03-22 11:42:32 +000055 printk(BIOS_DEBUG, "Setting RAM size to %ld MB\n", tomk / 1024);
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000056
57 /* Compute the top of low memory. */
58 tolmk = pci_tolm / 1024;
59
Richard Smithcb8eab42006-07-24 04:25:47 +000060 if (tolmk >= tomk) {
Myles Watson032a9652009-05-11 22:24:53 +000061 /* The PCI hole does not overlap the memory. */
Richard Smithcb8eab42006-07-24 04:25:47 +000062 tolmk = tomk;
63 }
Uwe Hermann1a9c8922007-04-01 17:24:03 +000064
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000065 /* Report the memory regions. */
Richard Smithcb8eab42006-07-24 04:25:47 +000066 idx = 10;
Uwe Hermann1a9c8922007-04-01 17:24:03 +000067 ram_resource(dev, idx++, 0, 640);
Uwe Hermannf5a6fd22007-05-27 23:31:31 +000068 ram_resource(dev, idx++, 768, tolmk - 768);
Myles Watson032a9652009-05-11 22:24:53 +000069
Keith Huid0301c12017-09-02 18:13:11 -040070 if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT))
71 set_late_cbmem_top(tomk * 1024);
Richard Smithcb8eab42006-07-24 04:25:47 +000072 }
Myles Watson894a3472010-06-09 22:41:35 +000073 assign_resources(dev->link_list);
Richard Smithcb8eab42006-07-24 04:25:47 +000074}
75
Richard Smithcb8eab42006-07-24 04:25:47 +000076static struct device_operations pci_domain_ops = {
Myles Watson032a9652009-05-11 22:24:53 +000077 .read_resources = pci_domain_read_resources,
Myles Watson29cc9ed2009-07-02 18:56:24 +000078 .set_resources = i440bx_domain_set_resources,
Myles Watson7eac4452010-06-17 16:16:56 +000079 .enable_resources = NULL,
80 .init = NULL,
Myles Watson032a9652009-05-11 22:24:53 +000081 .scan_bus = pci_domain_scan_bus,
82};
Richard Smithcb8eab42006-07-24 04:25:47 +000083
Elyes HAOUAS64d2d102018-02-09 08:43:01 +010084static void cpu_bus_init(struct device *dev)
Richard Smithcb8eab42006-07-24 04:25:47 +000085{
Myles Watson894a3472010-06-09 22:41:35 +000086 initialize_cpus(dev->link_list);
Richard Smithcb8eab42006-07-24 04:25:47 +000087}
88
Richard Smithcb8eab42006-07-24 04:25:47 +000089static struct device_operations cpu_bus_ops = {
Edward O'Callaghan9f744622014-10-31 08:12:34 +110090 .read_resources = DEVICE_NOOP,
91 .set_resources = DEVICE_NOOP,
92 .enable_resources = DEVICE_NOOP,
Myles Watson032a9652009-05-11 22:24:53 +000093 .init = cpu_bus_init,
94 .scan_bus = 0,
Richard Smithcb8eab42006-07-24 04:25:47 +000095};
96
97static void enable_dev(struct device *dev)
98{
Myles Watson032a9652009-05-11 22:24:53 +000099 /* Set the operations if it is a special bus type */
Stefan Reinauer4aff4452013-02-12 14:17:15 -0800100 if (dev->path.type == DEVICE_PATH_DOMAIN) {
Myles Watson032a9652009-05-11 22:24:53 +0000101 dev->ops = &pci_domain_ops;
Myles Watson032a9652009-05-11 22:24:53 +0000102 }
Stefan Reinauer0aa37c42013-02-12 15:20:54 -0800103 else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
Myles Watson032a9652009-05-11 22:24:53 +0000104 dev->ops = &cpu_bus_ops;
105 }
Richard Smithcb8eab42006-07-24 04:25:47 +0000106}
107
108struct chip_operations northbridge_intel_i440bx_ops = {
Uwe Hermannf5a6fd22007-05-27 23:31:31 +0000109 CHIP_NAME("Intel 82443BX (440BX) Northbridge")
Uwe Hermann1a9c8922007-04-01 17:24:03 +0000110 .enable_dev = enable_dev,
Richard Smithcb8eab42006-07-24 04:25:47 +0000111};