Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1 | /** @file |
| 2 | |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3 | Copyright (c) 2023, Intel Corporation. All rights reserved.<BR> |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 4 | |
| 5 | Redistribution and use in source and binary forms, with or without modification, |
| 6 | are permitted provided that the following conditions are met: |
| 7 | |
| 8 | * Redistributions of source code must retain the above copyright notice, this |
| 9 | list of conditions and the following disclaimer. |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, this |
| 11 | list of conditions and the following disclaimer in the documentation and/or |
| 12 | other materials provided with the distribution. |
| 13 | * Neither the name of Intel Corporation nor the names of its contributors may |
| 14 | be used to endorse or promote products derived from this software without |
| 15 | specific prior written permission. |
| 16 | |
| 17 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 18 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 19 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 20 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
| 21 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF |
| 27 | THE POSSIBILITY OF SUCH DAMAGE. |
| 28 | |
| 29 | This file is automatically generated. Please do NOT modify !!! |
| 30 | |
| 31 | **/ |
| 32 | |
| 33 | #ifndef __FSPMUPD_H__ |
| 34 | #define __FSPMUPD_H__ |
| 35 | |
| 36 | #include <FspUpd.h> |
| 37 | |
| 38 | #pragma pack(1) |
| 39 | |
| 40 | |
| 41 | #include <MemInfoHob.h> |
| 42 | |
| 43 | /// |
| 44 | /// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC. |
| 45 | /// |
| 46 | typedef struct { |
| 47 | UINT8 Revision; ///< Chipset Init Info Revision |
| 48 | UINT8 Rsvd[3]; ///< Reserved |
| 49 | UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table |
| 50 | UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table |
| 51 | } CHIPSET_INIT_INFO; |
| 52 | |
| 53 | |
| 54 | /** Fsp M Configuration |
| 55 | **/ |
| 56 | typedef struct { |
| 57 | |
| 58 | /** Offset 0x0040 - Platform Reserved Memory Size |
| 59 | The minimum platform memory size required to pass control into DXE |
| 60 | **/ |
| 61 | UINT64 PlatformMemorySize; |
| 62 | |
| 63 | /** Offset 0x0048 - SPD Data Length |
| 64 | Length of SPD Data |
| 65 | 0x100:256 Bytes, 0x200:512 Bytes, 0x400:1024 Bytes |
| 66 | **/ |
| 67 | UINT16 MemorySpdDataLen; |
| 68 | |
| 69 | /** Offset 0x004A - Enable above 4GB MMIO resource support |
| 70 | Enable/disable above 4GB MMIO resource support |
| 71 | $EN_DIS |
| 72 | **/ |
| 73 | UINT8 EnableAbove4GBMmio; |
| 74 | |
Bora Guvendik | 225e79b | 2022-05-31 10:51:17 -0700 | [diff] [blame] | 75 | /** Offset 0x004B - Enable/Disable CrashLog Device 10 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 76 | Enable(Default): Enable CPU CrashLog Device 10, Disable: Disable CPU CrashLog |
| 77 | $EN_DIS |
| 78 | **/ |
| 79 | UINT8 CpuCrashLogDevice; |
| 80 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 81 | /** Offset 0x004C - Memory SPD Pointer Controller 0 Channel 0 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 82 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 83 | **/ |
| 84 | UINT32 MemorySpdPtr000; |
| 85 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 86 | /** Offset 0x0050 - Memory SPD Pointer Controller 0 Channel 0 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 87 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 88 | **/ |
| 89 | UINT32 MemorySpdPtr001; |
| 90 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 91 | /** Offset 0x0054 - Memory SPD Pointer Controller 0 Channel 1 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 92 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 93 | **/ |
| 94 | UINT32 MemorySpdPtr010; |
| 95 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 96 | /** Offset 0x0058 - Memory SPD Pointer Controller 0 Channel 1 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 97 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 98 | **/ |
| 99 | UINT32 MemorySpdPtr011; |
| 100 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 101 | /** Offset 0x005C - Memory SPD Pointer Controller 0 Channel 2 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 102 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 103 | **/ |
| 104 | UINT32 MemorySpdPtr020; |
| 105 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 106 | /** Offset 0x0060 - Memory SPD Pointer Controller 0 Channel 2 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 107 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 108 | **/ |
| 109 | UINT32 MemorySpdPtr021; |
| 110 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 111 | /** Offset 0x0064 - Memory SPD Pointer Controller 0 Channel 3 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 112 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 113 | **/ |
| 114 | UINT32 MemorySpdPtr030; |
| 115 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 116 | /** Offset 0x0068 - Memory SPD Pointer Controller 0 Channel 3 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 117 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 118 | **/ |
| 119 | UINT32 MemorySpdPtr031; |
| 120 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 121 | /** Offset 0x006C - Memory SPD Pointer Controller 1 Channel 0 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 122 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 123 | **/ |
| 124 | UINT32 MemorySpdPtr100; |
| 125 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 126 | /** Offset 0x0070 - Memory SPD Pointer Controller 1 Channel 0 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 127 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 128 | **/ |
| 129 | UINT32 MemorySpdPtr101; |
| 130 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 131 | /** Offset 0x0074 - Memory SPD Pointer Controller 1 Channel 1 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 132 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 133 | **/ |
| 134 | UINT32 MemorySpdPtr110; |
| 135 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 136 | /** Offset 0x0078 - Memory SPD Pointer Controller 1 Channel 1 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 137 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 138 | **/ |
| 139 | UINT32 MemorySpdPtr111; |
| 140 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 141 | /** Offset 0x007C - Memory SPD Pointer Controller 1 Channel 2 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 142 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 143 | **/ |
| 144 | UINT32 MemorySpdPtr120; |
| 145 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 146 | /** Offset 0x0080 - Memory SPD Pointer Controller 1 Channel 2 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 147 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 148 | **/ |
| 149 | UINT32 MemorySpdPtr121; |
| 150 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 151 | /** Offset 0x0084 - Memory SPD Pointer Controller 1 Channel 3 Dimm 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 152 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 153 | **/ |
| 154 | UINT32 MemorySpdPtr130; |
| 155 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 156 | /** Offset 0x0088 - Memory SPD Pointer Controller 1 Channel 3 Dimm 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 157 | Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00 |
| 158 | **/ |
| 159 | UINT32 MemorySpdPtr131; |
| 160 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 161 | /** Offset 0x008C - RcompResistor settings |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 162 | Indicates RcompResistor settings: Board-dependent |
| 163 | **/ |
| 164 | UINT16 RcompResistor; |
| 165 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 166 | /** Offset 0x008E - RcompTarget settings |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 167 | RcompTarget settings: board-dependent |
| 168 | **/ |
| 169 | UINT16 RcompTarget[5]; |
| 170 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 171 | /** Offset 0x0098 - Dqs Map CPU to DRAM MC 0 CH 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 172 | Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 173 | **/ |
| 174 | UINT8 DqsMapCpu2DramMc0Ch0[2]; |
| 175 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 176 | /** Offset 0x009A - Dqs Map CPU to DRAM MC 0 CH 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 177 | Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 178 | **/ |
| 179 | UINT8 DqsMapCpu2DramMc0Ch1[2]; |
| 180 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 181 | /** Offset 0x009C - Dqs Map CPU to DRAM MC 0 CH 2 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 182 | Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| 183 | **/ |
| 184 | UINT8 DqsMapCpu2DramMc0Ch2[2]; |
| 185 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 186 | /** Offset 0x009E - Dqs Map CPU to DRAM MC 0 CH 3 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 187 | Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 188 | **/ |
| 189 | UINT8 DqsMapCpu2DramMc0Ch3[2]; |
| 190 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 191 | /** Offset 0x00A0 - Dqs Map CPU to DRAM MC 1 CH 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 192 | Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 193 | **/ |
| 194 | UINT8 DqsMapCpu2DramMc1Ch0[2]; |
| 195 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 196 | /** Offset 0x00A2 - Dqs Map CPU to DRAM MC 1 CH 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 197 | Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 198 | **/ |
| 199 | UINT8 DqsMapCpu2DramMc1Ch1[2]; |
| 200 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 201 | /** Offset 0x00A4 - Dqs Map CPU to DRAM MC 1 CH 2 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 202 | Set Dqs mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| 203 | **/ |
| 204 | UINT8 DqsMapCpu2DramMc1Ch2[2]; |
| 205 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 206 | /** Offset 0x00A6 - Dqs Map CPU to DRAM MC 1 CH 3 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 207 | Set Dqs mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 208 | **/ |
| 209 | UINT8 DqsMapCpu2DramMc1Ch3[2]; |
| 210 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 211 | /** Offset 0x00A8 - Dq Map CPU to DRAM MC 0 CH 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 212 | Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 213 | **/ |
| 214 | UINT8 DqMapCpu2DramMc0Ch0[16]; |
| 215 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 216 | /** Offset 0x00B8 - Dq Map CPU to DRAM MC 0 CH 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 217 | Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 218 | **/ |
| 219 | UINT8 DqMapCpu2DramMc0Ch1[16]; |
| 220 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 221 | /** Offset 0x00C8 - Dq Map CPU to DRAM MC 0 CH 2 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 222 | Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependet |
| 223 | **/ |
| 224 | UINT8 DqMapCpu2DramMc0Ch2[16]; |
| 225 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 226 | /** Offset 0x00D8 - Dq Map CPU to DRAM MC 0 CH 3 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 227 | Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 228 | **/ |
| 229 | UINT8 DqMapCpu2DramMc0Ch3[16]; |
| 230 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 231 | /** Offset 0x00E8 - Dq Map CPU to DRAM MC 1 CH 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 232 | Set Dq mapping relationship between CPU and DRAM, Channel 0: board-dependent |
| 233 | **/ |
| 234 | UINT8 DqMapCpu2DramMc1Ch0[16]; |
| 235 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 236 | /** Offset 0x00F8 - Dq Map CPU to DRAM MC 1 CH 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 237 | Set Dq mapping relationship between CPU and DRAM, Channel 1: board-dependent |
| 238 | **/ |
| 239 | UINT8 DqMapCpu2DramMc1Ch1[16]; |
| 240 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 241 | /** Offset 0x0108 - Dq Map CPU to DRAM MC 1 CH 2 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 242 | Set Dq mapping relationship between CPU and DRAM, Channel 2: board-dependent |
| 243 | **/ |
| 244 | UINT8 DqMapCpu2DramMc1Ch2[16]; |
| 245 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 246 | /** Offset 0x0118 - Dq Map CPU to DRAM MC 1 CH 3 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 247 | Set Dq mapping relationship between CPU and DRAM, Channel 3: board-dependent |
| 248 | **/ |
| 249 | UINT8 DqMapCpu2DramMc1Ch3[16]; |
| 250 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 251 | /** Offset 0x0128 - Dqs Pins Interleaved Setting |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 252 | Indicates DqPinsInterleaved setting: board-dependent |
| 253 | $EN_DIS |
| 254 | **/ |
| 255 | UINT8 DqPinsInterleaved; |
| 256 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 257 | /** Offset 0x0129 - Smram Mask |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 258 | The SMM Regions AB-SEG and/or H-SEG reserved |
| 259 | 0: Neither, 1:AB-SEG, 2:H-SEG, 3: Both |
| 260 | **/ |
| 261 | UINT8 SmramMask; |
| 262 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 263 | /** Offset 0x012A - Ibecc |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 264 | Enable/Disable Ibecc |
| 265 | $EN_DIS |
| 266 | **/ |
| 267 | UINT8 Ibecc; |
| 268 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 269 | /** Offset 0x012B - IbeccOperationMode |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 270 | In-Band ECC Operation Mode |
| 271 | 0:Protect base on address range, 1:Non-protected, 2:All protected |
| 272 | **/ |
| 273 | UINT8 IbeccOperationMode; |
| 274 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 275 | /** Offset 0x012C - IbeccProtectedRangeEnable |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 276 | In-Band ECC Protected Region Enable |
| 277 | $EN_DIS |
| 278 | **/ |
| 279 | UINT8 IbeccProtectedRangeEnable[8]; |
| 280 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 281 | /** Offset 0x0134 - IbeccProtectedRangeBase |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 282 | IBECC Protected Region Base |
| 283 | **/ |
| 284 | UINT32 IbeccProtectedRangeBase[8]; |
| 285 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 286 | /** Offset 0x0154 - IbeccProtectedRangeMask |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 287 | IBECC Protected Region Mask |
| 288 | **/ |
| 289 | UINT32 IbeccProtectedRangeMask[8]; |
| 290 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 291 | /** Offset 0x0174 - MRC Fast Boot |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 292 | Enables/Disable the MRC fast path thru the MRC |
| 293 | $EN_DIS |
| 294 | **/ |
| 295 | UINT8 MrcFastBoot; |
| 296 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 297 | /** Offset 0x0175 - Rank Margin Tool per Task |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 298 | This option enables the user to execute Rank Margin Tool per major training step |
| 299 | in the MRC. |
| 300 | $EN_DIS |
| 301 | **/ |
| 302 | UINT8 RmtPerTask; |
| 303 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 304 | /** Offset 0x0176 - Training Trace |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 305 | This option enables the trained state tracing feature in MRC. This feature will |
| 306 | print out the key training parameters state across major training steps. |
| 307 | $EN_DIS |
| 308 | **/ |
| 309 | UINT8 TrainTrace; |
| 310 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 311 | /** Offset 0x0177 - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 312 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 313 | UINT8 Reserved0; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 314 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 315 | /** Offset 0x0178 - Tseg Size |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 316 | Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build |
| 317 | 0x0400000:4MB, 0x01000000:16MB |
| 318 | **/ |
| 319 | UINT32 TsegSize; |
| 320 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 321 | /** Offset 0x017C - MMIO Size |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 322 | Size of MMIO space reserved for devices. 0(Default)=Auto, non-Zero=size in MB |
| 323 | **/ |
| 324 | UINT16 MmioSize; |
| 325 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 326 | /** Offset 0x017E - Probeless Trace |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 327 | Probeless Trace: 0=Disabled, 1=Enable. Enabling Probeless Trace will reserve 128MB. |
| 328 | This also requires IED to be enabled. |
| 329 | $EN_DIS |
| 330 | **/ |
| 331 | UINT8 ProbelessTrace; |
| 332 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 333 | /** Offset 0x017F - Enable SMBus |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 334 | Enable/disable SMBus controller. |
| 335 | $EN_DIS |
| 336 | **/ |
| 337 | UINT8 SmbusEnable; |
| 338 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 339 | /** Offset 0x0180 - Spd Address Tabl |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 340 | Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used |
| 341 | if SPD Address is 00 |
| 342 | **/ |
| 343 | UINT8 SpdAddressTable[16]; |
| 344 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 345 | /** Offset 0x0190 - Platform Debug Consent |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 346 | Enabled(All Probes+TraceHub) supports all probes with TraceHub enabled and blocks |
| 347 | s0ix\n |
| 348 | \n |
| 349 | Enabled(Low Power) does not support DCI OOB 4-wire and Tracehub is powergated by |
| 350 | default, s0ix is viable\n |
| 351 | \n |
| 352 | Manual:user needs to configure Advanced Debug Settings manually, aimed at advanced users |
| 353 | 0:Disabled, 2:Enabled (All Probes+TraceHub), 6:Enable (Low Power), 7:Manual |
| 354 | **/ |
| 355 | UINT8 PlatformDebugConsent; |
| 356 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 357 | /** Offset 0x0191 - DCI Enable |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 358 | Determine if to enable DCI debug from host |
| 359 | $EN_DIS |
| 360 | **/ |
| 361 | UINT8 DciEn; |
| 362 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 363 | /** Offset 0x0192 - DCI DbC Mode |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 364 | Disabled: Clear both USB2/3DBCEN; USB2: set USB2DBCEN; USB3: set USB3DBCEN; Both: |
| 365 | Set both USB2/3DBCEN; No Change: Comply with HW value |
| 366 | 0:Disabled, 1:USB2 DbC, 2:USB3 DbC, 3:Both, 4:No Change |
| 367 | **/ |
| 368 | UINT8 DciDbcMode; |
| 369 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 370 | /** Offset 0x0193 - Enable DCI ModPHY Power Gate |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 371 | DEPRECATED |
| 372 | $EN_DIS |
| 373 | **/ |
| 374 | UINT8 DciModphyPg; |
| 375 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 376 | /** Offset 0x0194 - USB3 Type-C UFP2DFP Kernel/Platform Debug Support |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 377 | This BIOS option enables kernel and platform debug for USB3 interface over a UFP |
| 378 | Type-C receptacle, select 'No Change' will do nothing to UFP2DFP setting. |
| 379 | 0:Disabled, 1:Enabled, 2:No Change |
| 380 | **/ |
| 381 | UINT8 DciUsb3TypecUfpDbg; |
| 382 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 383 | /** Offset 0x0195 - PCH Trace Hub Mode |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 384 | Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' |
| 385 | if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. |
| 386 | 0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode |
| 387 | **/ |
| 388 | UINT8 PchTraceHubMode; |
| 389 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 390 | /** Offset 0x0196 - PCH Trace Hub Memory Region 0 buffer Size |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 391 | Specify size of Pch trace memory region 0 buffer, the size can be 0, 1MB, 8MB, 64MB, |
| 392 | 128MB, 256MB, 512MB |
| 393 | 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB |
| 394 | **/ |
| 395 | UINT8 PchTraceHubMemReg0Size; |
| 396 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 397 | /** Offset 0x0197 - PCH Trace Hub Memory Region 1 buffer Size |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 398 | Specify size of Pch trace memory region 1 buffer, the size can be 0, 1MB, 8MB, 64MB, |
| 399 | 128MB, 256MB, 512MB |
| 400 | 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB |
| 401 | **/ |
| 402 | UINT8 PchTraceHubMemReg1Size; |
| 403 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 404 | /** Offset 0x0198 - HD Audio DMIC Link Clock Select |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 405 | Determines DMIC<N> Clock Source. 0: Both, 1: ClkA, 2: ClkB |
| 406 | 0: Both, 1: ClkA, 2: ClkB |
| 407 | **/ |
| 408 | UINT8 PchHdaAudioLinkDmicClockSelect[2]; |
| 409 | |
Bora Guvendik | c9f7e11 | 2023-01-31 18:59:47 -0800 | [diff] [blame^] | 410 | /** Offset 0x019A - Disable Tccold Handshake |
| 411 | Disable Tccold Handshake. <b>0: Do Nothing;</b> 1: Disable |
| 412 | $EN_DIS |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 413 | **/ |
Bora Guvendik | c9f7e11 | 2023-01-31 18:59:47 -0800 | [diff] [blame^] | 414 | UINT8 DisableDynamicTccoldHandshake; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 415 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 416 | /** Offset 0x019B - Reserved |
Selma Bensaid | 67ce1f2 | 2022-10-17 16:29:33 -0700 | [diff] [blame] | 417 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 418 | UINT8 Reserved2[4]; |
Selma Bensaid | 67ce1f2 | 2022-10-17 16:29:33 -0700 | [diff] [blame] | 419 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 420 | /** Offset 0x019F - State of X2APIC_OPT_OUT bit in the DMAR table |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 421 | 0=Disable/Clear, 1=Enable/Set |
| 422 | $EN_DIS |
| 423 | **/ |
| 424 | UINT8 X2ApicOptOut; |
| 425 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 426 | /** Offset 0x01A0 - State of DMA_CONTROL_GUARANTEE bit in the DMAR table |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 427 | 0=Disable/Clear, 1=Enable/Set |
| 428 | $EN_DIS |
| 429 | **/ |
| 430 | UINT8 DmaControlGuarantee; |
| 431 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 432 | /** Offset 0x01A1 - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 433 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 434 | UINT8 Reserved3[3]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 435 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 436 | /** Offset 0x01A4 - Base addresses for VT-d function MMIO access |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 437 | Base addresses for VT-d MMIO access per VT-d engine |
| 438 | **/ |
| 439 | UINT32 VtdBaseAddress[9]; |
| 440 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 441 | /** Offset 0x01C8 - Disable VT-d |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 442 | 0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled) |
| 443 | $EN_DIS |
| 444 | **/ |
| 445 | UINT8 VtdDisable; |
| 446 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 447 | /** Offset 0x01C9 - Vtd Programming for Igd |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 448 | 1=Enable/TRUE (Igd VT-d Bar programming enabled), 0=Disable/FLASE (Igd VT-d Bar |
| 449 | programming disabled) |
| 450 | $EN_DIS |
| 451 | **/ |
| 452 | UINT8 VtdIgdEnable; |
| 453 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 454 | /** Offset 0x01CA - Vtd Programming for Ipu |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 455 | 1=Enable/TRUE (Ipu VT-d Bar programming enabled), 0=Disable/FLASE (Ipu VT-d Bar |
| 456 | programming disabled) |
| 457 | $EN_DIS |
| 458 | **/ |
| 459 | UINT8 VtdIpuEnable; |
| 460 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 461 | /** Offset 0x01CB - Vtd Programming for Iop |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 462 | 1=Enable/TRUE (Iop VT-d Bar programming enabled), 0=Disable/FLASE (Iop VT-d Bar |
| 463 | programming disabled) |
| 464 | $EN_DIS |
| 465 | **/ |
| 466 | UINT8 VtdIopEnable; |
| 467 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 468 | /** Offset 0x01CC - Vtd Programming for ITbt |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 469 | DEPRECATED |
| 470 | $EN_DIS |
| 471 | **/ |
| 472 | UINT8 VtdItbtEnable; |
| 473 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 474 | /** Offset 0x01CD - Internal Graphics Pre-allocated Memory |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 475 | Size of memory preallocated for internal graphics. |
| 476 | 0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB, |
| 477 | 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, |
| 478 | 0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB |
| 479 | **/ |
| 480 | UINT8 IgdDvmt50PreAlloc; |
| 481 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 482 | /** Offset 0x01CE - Internal Graphics |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 483 | Enable/disable internal graphics. |
| 484 | $EN_DIS |
| 485 | **/ |
| 486 | UINT8 InternalGfx; |
| 487 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 488 | /** Offset 0x01CF - Aperture Size |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 489 | Select the Aperture Size. |
| 490 | 0:128 MB, 1:256 MB, 3:512 MB, 7:1024 MB, 15: 2048 MB |
| 491 | **/ |
| 492 | UINT8 ApertureSize; |
| 493 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 494 | /** Offset 0x01D0 - Board Type |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 495 | MrcBoardType, Options are 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, |
| 496 | 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server |
| 497 | 0:Mobile, 1:Desktop1Dpc, 2:Desktop2DpcDaisyChain, 3:Desktop2DpcTeeTopologyAsymmetrical, |
| 498 | 4:Desktop2DpcTeeTopology, 5:UltMobile, 7:UP Server |
| 499 | **/ |
| 500 | UINT8 UserBd; |
| 501 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 502 | /** Offset 0x01D1 - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 503 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 504 | UINT8 Reserved4; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 505 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 506 | /** Offset 0x01D2 - DDR Frequency Limit |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 507 | Maximum Memory Frequency Selections in Mhz. Options are 1067, 1333, 1600, 1867, |
| 508 | 2133, 2400, 2667, 2933 and 0 for Auto. |
| 509 | 1067:1067, 1333:1333, 1600:1600, 1867:1867, 2133:2133, 2400:2400, 2667:2667, 2933:2933, 0:Auto |
| 510 | **/ |
| 511 | UINT16 DdrFreqLimit; |
| 512 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 513 | /** Offset 0x01D4 - SA GV |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 514 | System Agent dynamic frequency support and when enabled memory will be training |
| 515 | at four different frequencies. |
| 516 | 0:Disabled, 1:FixedPoint0, 2:FixedPoint1, 3:FixedPoint2, 4:FixedPoint3, 5:Enabled |
| 517 | **/ |
| 518 | UINT8 SaGv; |
| 519 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 520 | /** Offset 0x01D5 - Memory Test on Warm Boot |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 521 | Run Base Memory Test on Warm Boot |
| 522 | 0:Disable, 1:Enable |
| 523 | **/ |
| 524 | UINT8 MemTestOnWarmBoot; |
| 525 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 526 | /** Offset 0x01D6 - DDR Speed Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 527 | DDR Frequency and Gear control for all SAGV points. |
| 528 | 0:Auto, 1:Manual |
| 529 | **/ |
| 530 | UINT8 DdrSpeedControl; |
| 531 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 532 | /** Offset 0x01D7 - Rank Margin Tool |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 533 | Enable/disable Rank Margin Tool. |
| 534 | $EN_DIS |
| 535 | **/ |
| 536 | UINT8 RMT; |
| 537 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 538 | /** Offset 0x01D8 - Controller 0 Channel 0 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 539 | Enable / Disable DIMMs on Controller 0 Channel 0 |
| 540 | $EN_DIS |
| 541 | **/ |
| 542 | UINT8 DisableMc0Ch0; |
| 543 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 544 | /** Offset 0x01D9 - Controller 0 Channel 1 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 545 | Enable / Disable DIMMs on Controller 0 Channel 1 |
| 546 | $EN_DIS |
| 547 | **/ |
| 548 | UINT8 DisableMc0Ch1; |
| 549 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 550 | /** Offset 0x01DA - Controller 0 Channel 2 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 551 | Enable / Disable DIMMs on Controller 0 Channel 2 |
| 552 | $EN_DIS |
| 553 | **/ |
| 554 | UINT8 DisableMc0Ch2; |
| 555 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 556 | /** Offset 0x01DB - Controller 0 Channel 3 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 557 | Enable / Disable DIMMs on Controller 0 Channel 3 |
| 558 | $EN_DIS |
| 559 | **/ |
| 560 | UINT8 DisableMc0Ch3; |
| 561 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 562 | /** Offset 0x01DC - Controller 1 Channel 0 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 563 | Enable / Disable DIMMs on Controller 1 Channel 0 |
| 564 | $EN_DIS |
| 565 | **/ |
| 566 | UINT8 DisableMc1Ch0; |
| 567 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 568 | /** Offset 0x01DD - Controller 1 Channel 1 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 569 | Enable / Disable DIMMs on Controller 1 Channel 1 |
| 570 | $EN_DIS |
| 571 | **/ |
| 572 | UINT8 DisableMc1Ch1; |
| 573 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 574 | /** Offset 0x01DE - Controller 1 Channel 2 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 575 | Enable / Disable DIMMs on Controller 1 Channel 2 |
| 576 | $EN_DIS |
| 577 | **/ |
| 578 | UINT8 DisableMc1Ch2; |
| 579 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 580 | /** Offset 0x01DF - Controller 1 Channel 3 DIMM Control |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 581 | Enable / Disable DIMMs on Controller 1 Channel 3 |
| 582 | $EN_DIS |
| 583 | **/ |
| 584 | UINT8 DisableMc1Ch3; |
| 585 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 586 | /** Offset 0x01E0 - Scrambler Support |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 587 | This option enables data scrambling in memory. |
| 588 | $EN_DIS |
| 589 | **/ |
| 590 | UINT8 ScramblerSupport; |
| 591 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 592 | /** Offset 0x01E1 - SPD Profile Selected |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 593 | Select DIMM timing profile. Options are 0:Default SPD Profile, 1:Custom Profile, |
| 594 | 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP Profile 3, 5:XMP User Profile 4, 6:XMP |
| 595 | User Profile 5 |
| 596 | 0:Default SPD Profile, 1:Custom Profile, 2:XMP Profile 1, 3:XMP Profile 2, 4:XMP |
| 597 | Profile 3, 5:XMP User Profile 4, 6:XMP User Profile 5 |
| 598 | **/ |
| 599 | UINT8 SpdProfileSelected; |
| 600 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 601 | /** Offset 0x01E2 - Memory Reference Clock |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 602 | 100MHz, 133MHz. |
| 603 | 0:133MHz, 1:100MHz |
| 604 | **/ |
| 605 | UINT8 RefClk; |
| 606 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 607 | /** Offset 0x01E3 - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 608 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 609 | UINT8 Reserved5; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 610 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 611 | /** Offset 0x01E4 - Memory Voltage |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 612 | DRAM voltage (Vdd) (supply voltage for input buffers and core logic of the DRAM |
| 613 | chips) in millivolts from 0 - default to 1435mv. |
| 614 | **/ |
| 615 | UINT16 VddVoltage; |
| 616 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 617 | /** Offset 0x01E6 - Memory Ratio |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 618 | Automatic or the frequency will equal ratio times reference clock. Set to Auto to |
| 619 | recalculate memory timings listed below. |
| 620 | 0:Auto, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 |
| 621 | **/ |
| 622 | UINT8 Ratio; |
| 623 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 624 | /** Offset 0x01E7 - tCL |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 625 | CAS Latency, 0: AUTO, max: 31. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 626 | == 1 (Custom Profile). |
| 627 | **/ |
| 628 | UINT8 tCL; |
| 629 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 630 | /** Offset 0x01E8 - tCWL |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 631 | Min CAS Write Latency Delay Time, 0: AUTO, max: 34. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 632 | == 1 (Custom Profile). |
| 633 | **/ |
| 634 | UINT8 tCWL; |
| 635 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 636 | /** Offset 0x01E9 - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 637 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 638 | UINT8 Reserved6; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 639 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 640 | /** Offset 0x01EA - tFAW |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 641 | Min Four Activate Window Delay Time, 0: AUTO, max: 63. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 642 | == 1 (Custom Profile). |
| 643 | **/ |
| 644 | UINT16 tFAW; |
| 645 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 646 | /** Offset 0x01EC - tRAS |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 647 | RAS Active Time, 0: AUTO, max: 64. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 648 | == 1 (Custom Profile). |
| 649 | **/ |
| 650 | UINT16 tRAS; |
| 651 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 652 | /** Offset 0x01EE - tRCD/tRP |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 653 | RAS to CAS delay time and Row Precharge delay time, 0: AUTO, max: 63. Only used |
| 654 | if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). |
| 655 | **/ |
| 656 | UINT8 tRCDtRP; |
| 657 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 658 | /** Offset 0x01EF - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 659 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 660 | UINT8 Reserved7; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 661 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 662 | /** Offset 0x01F0 - tREFI |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 663 | Refresh Interval, 0: AUTO, max: 65535. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 664 | == 1 (Custom Profile). |
| 665 | **/ |
| 666 | UINT16 tREFI; |
| 667 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 668 | /** Offset 0x01F2 - tRFC |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 669 | Min Refresh Recovery Delay Time, 0: AUTO, max: 1023. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 670 | == 1 (Custom Profile). |
| 671 | **/ |
| 672 | UINT16 tRFC; |
| 673 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 674 | /** Offset 0x01F4 - tRRD |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 675 | Min Row Active to Row Active Delay Time, 0: AUTO, max: 15. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 676 | == 1 (Custom Profile). |
| 677 | **/ |
| 678 | UINT8 tRRD; |
| 679 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 680 | /** Offset 0x01F5 - tRTP |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 681 | Min Internal Read to Precharge Command Delay Time, 0: AUTO, max: 15. DDR4 legal |
| 682 | values: 5, 6, 7, 8, 9, 10, 12. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 683 | == 1 (Custom Profile). |
| 684 | **/ |
| 685 | UINT8 tRTP; |
| 686 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 687 | /** Offset 0x01F6 - tWR |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 688 | Min Write Recovery Time, 0: AUTO, legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, |
| 689 | 20, 24, 30, 34, 40. Only used if FspmUpd->FspmConfig.SpdProfileSelected == 1 (Custom Profile). |
| 690 | 0:Auto, 5:5, 6:6, 7:7, 8:8, 10:10, 12:12, 14:14, 16:16, 18:18, 20:20, 24:24, 30:30, |
| 691 | 34:34, 40:40 |
| 692 | **/ |
| 693 | UINT8 tWR; |
| 694 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 695 | /** Offset 0x01F7 - tWTR |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 696 | Min Internal Write to Read Command Delay Time, 0: AUTO, max: 28. Only used if FspmUpd->FspmConfig.SpdProfileSelected |
| 697 | == 1 (Custom Profile). |
| 698 | **/ |
| 699 | UINT8 tWTR; |
| 700 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 701 | /** Offset 0x01F8 - NMode |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 702 | System command rate, range 0-2, 0 means auto, 1 = 1N, 2 = 2N |
| 703 | **/ |
| 704 | UINT8 NModeSupport; |
| 705 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 706 | /** Offset 0x01F9 - Enable Intel HD Audio (Azalia) |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 707 | 0: Disable, 1: Enable (Default) Azalia controller |
| 708 | $EN_DIS |
| 709 | **/ |
| 710 | UINT8 PchHdaEnable; |
| 711 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 712 | /** Offset 0x01FA - Enable PCH ISH Controller |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 713 | 0: Disable, 1: Enable (Default) ISH Controller |
| 714 | $EN_DIS |
| 715 | **/ |
| 716 | UINT8 PchIshEnable; |
| 717 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 718 | /** Offset 0x01FB - CPU Trace Hub Mode |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 719 | Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger' |
| 720 | if Trace Hub is used by target debugger software or 'Disable' trace hub functionality. |
| 721 | 0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode |
| 722 | **/ |
| 723 | UINT8 CpuTraceHubMode; |
| 724 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 725 | /** Offset 0x01FC - CPU Trace Hub Memory Region 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 726 | CPU Trace Hub Memory Region 0, The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, |
| 727 | 128MB, 256MB, 512MB |
| 728 | 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB |
| 729 | **/ |
| 730 | UINT8 CpuTraceHubMemReg0Size; |
| 731 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 732 | /** Offset 0x01FD - CPU Trace Hub Memory Region 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 733 | CPU Trace Hub Memory Region 1. The avaliable memory size is : 0MB, 1MB, 8MB, 64MB, |
| 734 | 128MB, 256MB, 512MB |
| 735 | 0:0, 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB |
| 736 | **/ |
| 737 | UINT8 CpuTraceHubMemReg1Size; |
| 738 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 739 | /** Offset 0x01FE - SAGV Gear Ratio |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 740 | Gear Selection for SAGV points. 0 - Auto, 1-1 Gear 1, 2-Gear 2 |
| 741 | **/ |
| 742 | UINT8 SaGvGear[4]; |
| 743 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 744 | /** Offset 0x0202 - SAGV Frequency |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 745 | SAGV Frequency per point in Mhz. 0 for Auto and a ratio of 133/100MHz: 1333/1300. |
| 746 | **/ |
| 747 | UINT16 SaGvFreq[4]; |
| 748 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 749 | /** Offset 0x020A - SAGV Disabled Gear Ratio |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 750 | Gear Selection for SAGV Disabled. 0 - Auto, 1-1 Gear 1, 2-Gear 2 |
| 751 | **/ |
| 752 | UINT8 GearRatio; |
| 753 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 754 | /** Offset 0x020B - HECI Timeouts |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 755 | 0: Disable, 1: Enable (Default) timeout check for HECI |
| 756 | $EN_DIS |
| 757 | **/ |
| 758 | UINT8 HeciTimeouts; |
| 759 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 760 | /** Offset 0x020C - HECI1 BAR address |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 761 | BAR address of HECI1 |
| 762 | **/ |
| 763 | UINT32 Heci1BarAddress; |
| 764 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 765 | /** Offset 0x0210 - HECI2 BAR address |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 766 | BAR address of HECI2 |
| 767 | **/ |
| 768 | UINT32 Heci2BarAddress; |
| 769 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 770 | /** Offset 0x0214 - HECI3 BAR address |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 771 | BAR address of HECI3 |
| 772 | **/ |
| 773 | UINT32 Heci3BarAddress; |
| 774 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 775 | /** Offset 0x0218 - HG dGPU Power Delay |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 776 | HG dGPU delay interval after power enabling: 0=Minimal, 1000=Maximum, default is |
| 777 | 300=300 microseconds |
| 778 | **/ |
| 779 | UINT16 HgDelayAfterPwrEn; |
| 780 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 781 | /** Offset 0x021A - HG dGPU Reset Delay |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 782 | HG dGPU delay interval for Reset complete: 0=Minimal, 1000=Maximum, default is 100=100 |
| 783 | microseconds |
| 784 | **/ |
| 785 | UINT16 HgDelayAfterHoldReset; |
| 786 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 787 | /** Offset 0x021C - MMIO size adjustment for AUTO mode |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 788 | Positive number means increasing MMIO size, Negative value means decreasing MMIO |
| 789 | size: 0 (Default)=no change to AUTO mode MMIO size |
| 790 | **/ |
| 791 | UINT16 MmioSizeAdjustment; |
| 792 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 793 | /** Offset 0x021E - PCIe ASPM programming will happen in relation to the Oprom |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 794 | Select when PCIe ASPM programming will happen in relation to the Oprom. Before(0x0)(Default): |
| 795 | Do PCIe ASPM programming before Oprom, After(0x1): Do PCIe ASPM programming after |
| 796 | Oprom, requires an SMI handler to save/restore ASPM settings during S3 resume |
| 797 | 0:Before, 1:After |
| 798 | **/ |
| 799 | UINT8 InitPcieAspmAfterOprom; |
| 800 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 801 | /** Offset 0x021F - Selection of the primary display device |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 802 | 0=iGFX, 1=PEG, 2=PCIe Graphics on PCH, 3(Default)=AUTO, 4=Hybrid Graphics |
| 803 | 0:iGFX, 1:PEG, 2:PCIe Graphics on PCH, 3:AUTO, 4:Hybrid Graphics |
| 804 | **/ |
| 805 | UINT8 PrimaryDisplay; |
| 806 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 807 | /** Offset 0x0220 - Selection of PSMI Region size |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 808 | 0=32MB, 1=288MB, 2=544MB, 3=800MB, 4=1024MB Default is 0 |
| 809 | 0:32MB, 1:288MB, 2:544MB, 3:800MB, 4:1024MB |
| 810 | **/ |
| 811 | UINT8 PsmiRegionSize; |
| 812 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 813 | /** Offset 0x0221 - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 814 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 815 | UINT8 Reserved8; |
| 816 | |
| 817 | /** Offset 0x0222 - Reserved |
| 818 | **/ |
| 819 | UINT8 Reserved9[2]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 820 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 821 | /** Offset 0x0224 - Temporary MMIO address for GMADR |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 822 | Obsolete field now and it has been extended to 64 bit address, used GmAdr64 |
| 823 | **/ |
| 824 | UINT32 GmAdr; |
| 825 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 826 | /** Offset 0x0228 - Temporary MMIO address for GTTMMADR |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 827 | The reference code will use this as Temporary MMIO address space to access GTTMMADR |
| 828 | Registers.Platform should provide conflict free Temporary MMIO Range: GttMmAdr |
| 829 | to (GttMmAdr + 2MB MMIO + 6MB Reserved + GttSize). Default is (GmAdr - (2MB MMIO |
| 830 | + 6MB Reserved + GttSize)) to (GmAdr - 0x1) (Where GttSize = 8MB) |
| 831 | **/ |
| 832 | UINT32 GttMmAdr; |
| 833 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 834 | /** Offset 0x022C - Selection of iGFX GTT Memory size |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 835 | 1=2MB, 2=4MB, 3=8MB, Default is 3 |
| 836 | 1:2MB, 2:4MB, 3:8MB |
| 837 | **/ |
| 838 | UINT16 GttSize; |
| 839 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 840 | /** Offset 0x022E - Hybrid Graphics GPIO information for PEG 0 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 841 | Hybrid Graphics GPIO information for PEG 0, for Reset, power and wake GPIOs |
| 842 | **/ |
| 843 | UINT8 CpuPcie0Rtd3Gpio[24]; |
| 844 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 845 | /** Offset 0x0246 - Enable/Disable MRC TXT dependency |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 846 | When enabled MRC execution will wait for TXT initialization to be done first. Disabled(0x0)(Default): |
| 847 | MRC will not wait for TXT initialization, Enabled(0x1): MRC will wait for TXT initialization |
| 848 | $EN_DIS |
| 849 | **/ |
| 850 | UINT8 TxtImplemented; |
| 851 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 852 | /** Offset 0x0247 - Enable/Disable SA OcSupport |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 853 | Enable: Enable SA OcSupport, Disable(Default): Disable SA OcSupport |
| 854 | $EN_DIS |
| 855 | **/ |
| 856 | UINT8 SaOcSupport; |
| 857 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 858 | /** Offset 0x0248 - GT slice Voltage Mode |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 859 | 0(Default): Adaptive, 1: Override |
| 860 | 0: Adaptive, 1: Override |
| 861 | **/ |
| 862 | UINT8 GtVoltageMode; |
| 863 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 864 | /** Offset 0x0249 - Maximum GTs turbo ratio override |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 865 | 0(Default)=Minimal/Auto, 60=Maximum |
| 866 | **/ |
| 867 | UINT8 GtMaxOcRatio; |
| 868 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 869 | /** Offset 0x024A - The voltage offset applied to GT slice |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 870 | 0(Default)=Minimal, 1000=Maximum |
| 871 | **/ |
| 872 | UINT16 GtVoltageOffset; |
| 873 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 874 | /** Offset 0x024C - The GT slice voltage override which is applied to the entire range of GT frequencies |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 875 | 0(Default)=Minimal, 2000=Maximum |
| 876 | **/ |
| 877 | UINT16 GtVoltageOverride; |
| 878 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 879 | /** Offset 0x024E - adaptive voltage applied during turbo frequencies |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 880 | 0(Default)=Minimal, 2000=Maximum |
| 881 | **/ |
| 882 | UINT16 GtExtraTurboVoltage; |
| 883 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 884 | /** Offset 0x0250 - voltage offset applied to the SA |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 885 | 0(Default)=Minimal, 1000=Maximum |
| 886 | **/ |
| 887 | UINT16 SaVoltageOffset; |
| 888 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 889 | /** Offset 0x0252 - PCIe root port Function number for Hybrid Graphics dGPU |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 890 | Root port Index number to indicate which PCIe root port has dGPU |
| 891 | **/ |
| 892 | UINT8 RootPortIndex; |
| 893 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 894 | /** Offset 0x0253 - Realtime Memory Timing |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 895 | 0(Default): Disabled, 1: Enabled. When enabled, it will allow the system to perform |
| 896 | realtime memory timing changes after MRC_DONE. |
| 897 | 0: Disabled, 1: Enabled |
| 898 | **/ |
| 899 | UINT8 RealtimeMemoryTiming; |
| 900 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 901 | /** Offset 0x0254 - iTBT PCIe Multiple Segment setting |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 902 | DEPRECATED |
| 903 | $EN_DIS |
| 904 | **/ |
| 905 | UINT8 PcieMultipleSegmentEnabled; |
| 906 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 907 | /** Offset 0x0255 - Enable/Disable SA IPU |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 908 | Enable(Default): Enable SA IPU, Disable: Disable SA IPU |
| 909 | $EN_DIS |
| 910 | **/ |
| 911 | UINT8 SaIpuEnable; |
| 912 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 913 | /** Offset 0x0256 - Lane Used of CSI port |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 914 | Lane Used of each CSI port |
| 915 | 1:x1, 2:x2, 3:x3, 4:x4, 8:x8 |
| 916 | **/ |
| 917 | UINT8 IpuLaneUsed[8]; |
| 918 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 919 | /** Offset 0x025E - Lane Used of CSI port |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 920 | Speed of each CSI port |
| 921 | 0:Sensor default, 1:<416Mbps, 2:<1.5Gbps, 3:<2Gbps, 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps |
| 922 | **/ |
| 923 | UINT8 CsiSpeed[8]; |
| 924 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 925 | /** Offset 0x0266 - IMGU CLKOUT Configuration |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 926 | The configuration of IMGU CLKOUT, 0: Disable;<b>1: Enable</b>. |
| 927 | $EN_DIS |
| 928 | **/ |
| 929 | UINT8 ImguClkOutEn[6]; |
| 930 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 931 | /** Offset 0x026C - Enable PCIE RP Mask |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 932 | Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 |
| 933 | for port1, bit1 for port2, and so on. |
| 934 | **/ |
| 935 | UINT32 CpuPcieRpEnableMask; |
| 936 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 937 | /** Offset 0x0270 - Assertion on Link Down GPIOs |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 938 | GPIO Assertion on Link Down. Disabled(0x0)(Default): Disable assertion on Link Down |
| 939 | GPIOs, Enabled(0x1): Enable assertion on Link Down GPIOs |
| 940 | 0:Disable, 1:Enable |
| 941 | **/ |
| 942 | UINT8 CpuPcieRpLinkDownGpios; |
| 943 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 944 | /** Offset 0x0271 - Enable ClockReq Messaging |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 945 | ClockReq Messaging. Disabled(0x0): Disable ClockReq Messaging, Enabled(0x1)(Default): |
| 946 | Enable ClockReq Messaging |
| 947 | 0:Disable, 1:Enable |
| 948 | **/ |
| 949 | UINT8 CpuPcieRpClockReqMsgEnable[3]; |
| 950 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 951 | /** Offset 0x0274 - PCIE RP Pcie Speed |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 952 | Determines each PCIE Port speed capability. 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; |
| 953 | 4: Gen4 (see: CPU_PCIE_SPEED). |
| 954 | **/ |
| 955 | UINT8 CpuPcieRpPcieSpeed[4]; |
| 956 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 957 | /** Offset 0x0278 - Selection of PSMI Support On/Off |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 958 | 0(Default) = FALSE, 1 = TRUE. When TRUE, it will allow the PSMI Support |
| 959 | $EN_DIS |
| 960 | **/ |
| 961 | UINT8 GtPsmiSupport; |
| 962 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 963 | /** Offset 0x0279 - Program GPIOs for LFP on DDI port-A device |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 964 | 0=Disabled,1(Default)=eDP, 2=MIPI DSI |
| 965 | 0:Disabled, 1:eDP, 2:MIPI DSI |
| 966 | **/ |
| 967 | UINT8 DdiPortAConfig; |
| 968 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 969 | /** Offset 0x027A - Program GPIOs for LFP on DDI port-B device |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 970 | 0(Default)=Disabled,1=eDP, 2=MIPI DSI |
| 971 | 0:Disabled, 1:eDP, 2:MIPI DSI |
| 972 | **/ |
| 973 | UINT8 DdiPortBConfig; |
| 974 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 975 | /** Offset 0x027B - Enable or disable HPD of DDI port A |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 976 | 0(Default)=Disable, 1=Enable |
| 977 | $EN_DIS |
| 978 | **/ |
| 979 | UINT8 DdiPortAHpd; |
| 980 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 981 | /** Offset 0x027C - Enable or disable HPD of DDI port B |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 982 | 0=Disable, 1(Default)=Enable |
| 983 | $EN_DIS |
| 984 | **/ |
| 985 | UINT8 DdiPortBHpd; |
| 986 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 987 | /** Offset 0x027D - Enable or disable HPD of DDI port C |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 988 | 0(Default)=Disable, 1=Enable |
| 989 | $EN_DIS |
| 990 | **/ |
| 991 | UINT8 DdiPortCHpd; |
| 992 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 993 | /** Offset 0x027E - Enable or disable HPD of DDI port 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 994 | 0=Disable, 1(Default)=Enable |
| 995 | $EN_DIS |
| 996 | **/ |
| 997 | UINT8 DdiPort1Hpd; |
| 998 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 999 | /** Offset 0x027F - Enable or disable HPD of DDI port 2 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1000 | 0(Default)=Disable, 1=Enable |
| 1001 | $EN_DIS |
| 1002 | **/ |
| 1003 | UINT8 DdiPort2Hpd; |
| 1004 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1005 | /** Offset 0x0280 - Enable or disable HPD of DDI port 3 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1006 | 0(Default)=Disable, 1=Enable |
| 1007 | $EN_DIS |
| 1008 | **/ |
| 1009 | UINT8 DdiPort3Hpd; |
| 1010 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1011 | /** Offset 0x0281 - Enable or disable HPD of DDI port 4 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1012 | 0(Default)=Disable, 1=Enable |
| 1013 | $EN_DIS |
| 1014 | **/ |
| 1015 | UINT8 DdiPort4Hpd; |
| 1016 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1017 | /** Offset 0x0282 - Enable or disable DDC of DDI port A |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1018 | 0(Default)=Disable, 1=Enable |
| 1019 | $EN_DIS |
| 1020 | **/ |
| 1021 | UINT8 DdiPortADdc; |
| 1022 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1023 | /** Offset 0x0283 - Enable or disable DDC of DDI port B |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1024 | 0=Disable, 1(Default)=Enable |
| 1025 | $EN_DIS |
| 1026 | **/ |
| 1027 | UINT8 DdiPortBDdc; |
| 1028 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1029 | /** Offset 0x0284 - Enable or disable DDC of DDI port C |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1030 | 0(Default)=Disable, 1=Enable |
| 1031 | $EN_DIS |
| 1032 | **/ |
| 1033 | UINT8 DdiPortCDdc; |
| 1034 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1035 | /** Offset 0x0285 - Enable DDC setting of DDI Port 1 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1036 | 0(Default)=Disable, 1=Enable |
| 1037 | $EN_DIS |
| 1038 | **/ |
| 1039 | UINT8 DdiPort1Ddc; |
| 1040 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1041 | /** Offset 0x0286 - Enable DDC setting of DDI Port 2 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1042 | 0(Default)=Disable, 1=Enable |
| 1043 | $EN_DIS |
| 1044 | **/ |
| 1045 | UINT8 DdiPort2Ddc; |
| 1046 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1047 | /** Offset 0x0287 - Enable DDC setting of DDI Port 3 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1048 | 0(Default)=Disable, 1=Enable |
| 1049 | $EN_DIS |
| 1050 | **/ |
| 1051 | UINT8 DdiPort3Ddc; |
| 1052 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1053 | /** Offset 0x0288 - Enable DDC setting of DDI Port 4 |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1054 | 0(Default)=Disable, 1=Enable |
| 1055 | $EN_DIS |
| 1056 | **/ |
| 1057 | UINT8 DdiPort4Ddc; |
| 1058 | |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 1059 | /** Offset 0x0289 - Reserved |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1060 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1061 | UINT8 Reserved10[7]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1062 | |
| 1063 | /** Offset 0x0290 - Temporary MMIO address for GMADR |
| 1064 | The reference code will use this as Temporary MMIO address space to access GMADR |
| 1065 | Registers.Platform should provide conflict free Temporary MMIO Range: GmAdr to |
| 1066 | (GmAdr + ApertureSize). Default is (PciExpressBaseAddress - ApertureSize) to (PciExpressBaseAddress |
| 1067 | - 0x1) (Where ApertureSize = 256MB, 512MB, 1024MB and 2048MB) |
| 1068 | **/ |
| 1069 | UINT64 GmAdr64; |
| 1070 | |
| 1071 | /** Offset 0x0298 - Per-core HT Disable |
| 1072 | Defines the per-core HT disable mask where: 1 - Disable selected logical core HT, |
| 1073 | 0 - is ignored. Input is in HEX and each bit maps to a logical core. Ex. A value |
| 1074 | of '1F' would disable HT for cores 4,3,2,1 and 0. Default is 0, all cores have |
| 1075 | HT enabled. Range is 0 - 0x7F for max 8 cores. You can only disable up to MAX_CORE_COUNT - 1. |
| 1076 | **/ |
| 1077 | UINT16 PerCoreHtDisable; |
| 1078 | |
| 1079 | /** Offset 0x029A - SA/Uncore voltage mode |
| 1080 | SA/Uncore voltage mode; <b>0: Adaptive</b>; 1: Override. |
| 1081 | $EN_DIS |
| 1082 | **/ |
| 1083 | UINT8 SaVoltageMode; |
| 1084 | |
| 1085 | /** Offset 0x029B - Reserved |
| 1086 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1087 | UINT8 Reserved11; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1088 | |
| 1089 | /** Offset 0x029C - SA/Uncore Voltage Override |
| 1090 | The SA/Uncore voltage override applicable when SA/Uncore voltage mode is in Override |
| 1091 | mode. Valid Range 0 to 2000 |
| 1092 | **/ |
| 1093 | UINT16 SaVoltageOverride; |
| 1094 | |
| 1095 | /** Offset 0x029E - SA/Uncore Extra Turbo voltage |
| 1096 | Extra Turbo voltage applicable when SA/Uncore voltage mode is in Adaptive mode. |
| 1097 | Valid Range 0 to 2000 |
| 1098 | **/ |
| 1099 | UINT16 SaExtraTurboVoltage; |
| 1100 | |
| 1101 | /** Offset 0x02A0 - Thermal Velocity Boost Ratio clipping |
| 1102 | 0(Default): Disabled, 1: Enabled. This service controls Core frequency reduction |
| 1103 | caused by high package temperatures for processors that implement the Intel Thermal |
| 1104 | Velocity Boost (TVB) feature |
| 1105 | 0: Disabled, 1: Enabled |
| 1106 | **/ |
| 1107 | UINT8 TvbRatioClipping; |
| 1108 | |
| 1109 | /** Offset 0x02A1 - Thermal Velocity Boost voltage optimization |
| 1110 | 0: Disabled, 1: Enabled(Default). This service controls thermal based voltage optimizations |
| 1111 | for processors that implement the Intel Thermal Velocity Boost (TVB) feature. |
| 1112 | 0: Disabled, 1: Enabled |
| 1113 | **/ |
| 1114 | UINT8 TvbVoltageOptimization; |
| 1115 | |
| 1116 | /** Offset 0x02A2 - Reserved |
| 1117 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1118 | UINT8 Reserved12; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1119 | |
| 1120 | /** Offset 0x02A3 - Reserved |
| 1121 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1122 | UINT8 Reserved13; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1123 | |
| 1124 | /** Offset 0x02A4 - Reserved |
| 1125 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1126 | UINT16 Reserved14; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1127 | |
| 1128 | /** Offset 0x02A6 - Reserved |
| 1129 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1130 | UINT16 Reserved15; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1131 | |
| 1132 | /** Offset 0x02A8 - Reserved |
| 1133 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1134 | UINT8 Reserved16[4]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1135 | |
| 1136 | /** Offset 0x02AC - Reserved |
| 1137 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1138 | UINT8 Reserved17; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1139 | |
| 1140 | /** Offset 0x02AD - Reserved |
| 1141 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1142 | UINT8 Reserved18; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1143 | |
| 1144 | /** Offset 0x02AE - Reserved |
| 1145 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1146 | UINT8 Reserved19; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1147 | |
| 1148 | /** Offset 0x02AF - Reserved |
| 1149 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1150 | UINT8 Reserved20; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1151 | |
| 1152 | /** Offset 0x02B0 - Reserved |
| 1153 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1154 | UINT8 Reserved21; |
Selma Bensaid | eb17259 | 2022-09-15 18:37:41 -0700 | [diff] [blame] | 1155 | |
| 1156 | /** Offset 0x02B1 - Reserved |
| 1157 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1158 | UINT8 Reserved22[96]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1159 | |
| 1160 | /** Offset 0x0311 - Enable Gt CLOS |
| 1161 | 0(Default)=Disable, 1=Enable |
| 1162 | $EN_DIS |
| 1163 | **/ |
| 1164 | UINT8 GtClosEnable; |
| 1165 | |
| 1166 | /** Offset 0x0312 - DMI Max Link Speed |
| 1167 | Auto (Default)(0x0): Maximum possible link speed, Gen1(0x1): Limit Link to Gen1 |
| 1168 | Speed, Gen2(0x2): Limit Link to Gen2 Speed, Gen3(0x3):Limit Link to Gen3 Speed |
| 1169 | 0:Auto, 1:Gen1, 2:Gen2, 3:Gen3 |
| 1170 | **/ |
| 1171 | UINT8 DmiMaxLinkSpeed; |
| 1172 | |
| 1173 | /** Offset 0x0313 - DMI Equalization Phase 2 |
| 1174 | DMI Equalization Phase 2. (0x0): Disable phase 2, (0x1): Enable phase 2, (0x2)(Default): |
| 1175 | AUTO - Use the current default method |
| 1176 | 0:Disable phase2, 1:Enable phase2, 2:Auto |
| 1177 | **/ |
| 1178 | UINT8 DmiGen3EqPh2Enable; |
| 1179 | |
| 1180 | /** Offset 0x0314 - DMI Gen3 Equalization Phase3 |
| 1181 | DMI Gen3 Equalization Phase3. Auto(0x0)(Default): Use the current default method, |
| 1182 | HwEq(0x1): Use Adaptive Hardware Equalization, SwEq(0x2): Use Adaptive Software |
| 1183 | Equalization (Implemented in BIOS Reference Code), Static(0x3): Use the Static |
| 1184 | EQs provided in DmiGen3EndPointPreset array for Phase1 AND Phase3 (Instead of just |
| 1185 | Phase1), Disabled(0x4): Bypass Equalization Phase 3 |
| 1186 | 0:Auto, 1:HwEq, 2:SwEq, 3:StaticEq, 4:BypassPhase3 |
| 1187 | **/ |
| 1188 | UINT8 DmiGen3EqPh3Method; |
| 1189 | |
| 1190 | /** Offset 0x0315 - Enable/Disable DMI GEN3 Static EQ Phase1 programming |
| 1191 | Program DMI Gen3 EQ Phase1 Static Presets. Disabled(0x0): Disable EQ Phase1 Static |
| 1192 | Presets Programming, Enabled(0x1)(Default): Enable EQ Phase1 Static Presets Programming |
| 1193 | $EN_DIS |
| 1194 | **/ |
| 1195 | UINT8 DmiGen3ProgramStaticEq; |
| 1196 | |
| 1197 | /** Offset 0x0316 - DeEmphasis control for DMI |
| 1198 | DeEmphasis control for DMI. 0=-6dB, 1(Default)=-3.5 dB |
| 1199 | 0: -6dB, 1: -3.5dB |
| 1200 | **/ |
| 1201 | UINT8 DmiDeEmphasis; |
| 1202 | |
| 1203 | /** Offset 0x0317 - DMI Gen3 Root port preset values per lane |
| 1204 | Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane |
| 1205 | **/ |
| 1206 | UINT8 DmiGen3RootPortPreset[8]; |
| 1207 | |
| 1208 | /** Offset 0x031F - DMI Gen3 End port preset values per lane |
| 1209 | Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is default for each lane |
| 1210 | **/ |
| 1211 | UINT8 DmiGen3EndPointPreset[8]; |
| 1212 | |
| 1213 | /** Offset 0x0327 - DMI Gen3 End port Hint values per lane |
| 1214 | Used for programming DMI Gen3 Hint values per lane. Range: 0-6, 2 is default for each lane |
| 1215 | **/ |
| 1216 | UINT8 DmiGen3EndPointHint[8]; |
| 1217 | |
| 1218 | /** Offset 0x032F - DMI Gen3 RxCTLEp per-Bundle control |
| 1219 | Range: 0-15, 0 is default for each bundle, must be specified based upon platform design |
| 1220 | **/ |
| 1221 | UINT8 DmiGen3RxCtlePeaking[4]; |
| 1222 | |
| 1223 | /** Offset 0x0333 - DMI ASPM Configuration:{Combo |
| 1224 | Set ASPM Configuration |
| 1225 | 0:Disabled, 1:L0s, 2:L1, 3:L1L0s |
| 1226 | **/ |
| 1227 | UINT8 DmiAspm; |
| 1228 | |
| 1229 | /** Offset 0x0334 - Enable/Disable DMI GEN3 Hardware Eq |
| 1230 | Enable/Disable DMI GEN3 Hardware Eq. Disabled(0x0)(Default): Disable Hardware Eq, |
| 1231 | Enabled(0x1): Enable EQ Phase1 Static Presets Programming |
| 1232 | $EN_DIS |
| 1233 | **/ |
| 1234 | UINT8 DmiHweq; |
| 1235 | |
| 1236 | /** Offset 0x0335 - Enable/Disable CPU DMI GEN3 Phase 23 Bypass |
| 1237 | CPU DMI GEN3 Phase 23 Bypass. Disabled(0x0)(Default): Disable Phase 23 Bypass, Enabled(0x1): |
| 1238 | Enable Phase 23 Bypass |
| 1239 | $EN_DIS |
| 1240 | **/ |
| 1241 | UINT8 Gen3EqPhase23Bypass; |
| 1242 | |
| 1243 | /** Offset 0x0336 - Enable/Disable CPU DMI GEN3 Phase 3 Bypass |
| 1244 | CPU DMI GEN3 Phase 3 Bypass. Disabled(0x0)(Default): Disable Phase 3 Bypass, Enabled(0x1): |
| 1245 | Enable Phase 3 Bypass |
| 1246 | $EN_DIS |
| 1247 | **/ |
| 1248 | UINT8 Gen3EqPhase3Bypass; |
| 1249 | |
| 1250 | /** Offset 0x0337 - Enable/Disable CPU DMI Gen3 EQ Local Transmitter Coefficient Override Enable |
| 1251 | Program Gen3 EQ Local Transmitter Coefficient Override. Disabled(0x0)(Default): |
| 1252 | Disable Local Transmitter Coefficient Override, Enabled(0x1): Enable Local Transmitter |
| 1253 | Coefficient Override |
| 1254 | $EN_DIS |
| 1255 | **/ |
| 1256 | UINT8 Gen3LtcoEnable; |
| 1257 | |
| 1258 | /** Offset 0x0338 - Enable/Disable CPU DMI Gen3 EQ Remote Transmitter Coefficient/Preset Override Enable |
| 1259 | Program Remote Transmitter Coefficient/Preset Override. Disabled(0x0)(Default): |
| 1260 | Disable Remote Transmitter Coefficient/Preset Override, Enabled(0x1): Enable Remote |
| 1261 | Transmitter Coefficient/Preset Override |
| 1262 | $EN_DIS |
| 1263 | **/ |
| 1264 | UINT8 Gen3RtcoRtpoEnable; |
| 1265 | |
| 1266 | /** Offset 0x0339 - DMI Gen3 Transmitter Pre-Cursor Coefficient |
| 1267 | Used for programming DMI Gen3 Transmitter Pre-Cursor Coefficient . Range: 0-10, |
| 1268 | 2 is default for each lane |
| 1269 | **/ |
| 1270 | UINT8 DmiGen3Ltcpre[8]; |
| 1271 | |
| 1272 | /** Offset 0x0341 - DMI Gen3 Transmitter Post-Cursor Coefficient |
| 1273 | Used for programming Transmitter Post-Cursor Coefficient. Range: 0-9, 2 is default |
| 1274 | for each lane |
| 1275 | **/ |
| 1276 | UINT8 DmiGen3Ltcpo[8]; |
| 1277 | |
| 1278 | /** Offset 0x0349 - PCIE Hw Eq Gen3 CoeffList Cm |
| 1279 | CPU_PCIE_EQ_PARAM. Coefficient C-1. |
| 1280 | **/ |
| 1281 | UINT8 CpuDmiHwEqGen3CoeffListCm[8]; |
| 1282 | |
| 1283 | /** Offset 0x0351 - PCIE Hw Eq Gen3 CoeffList Cp |
| 1284 | CPU_PCIE_EQ_PARAM. Coefficient C+1. |
| 1285 | **/ |
| 1286 | UINT8 CpuDmiHwEqGen3CoeffListCp[8]; |
| 1287 | |
| 1288 | /** Offset 0x0359 - Enable/Disable DMI GEN3 DmiGen3DsPresetEnable |
| 1289 | Enable/Disable DMI GEN3 DmiGen3DsPreset. Auto(0x0)(Default): DmiGen3DsPresetEnable, |
| 1290 | Manual(0x1): Enable DmiGen3DsPresetEnable |
| 1291 | $EN_DIS |
| 1292 | **/ |
| 1293 | UINT8 DmiGen3DsPresetEnable; |
| 1294 | |
| 1295 | /** Offset 0x035A - DMI Gen3 Root port preset Rx values per lane |
| 1296 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 1 is default |
| 1297 | for each lane |
| 1298 | **/ |
| 1299 | UINT8 DmiGen3DsPortRxPreset[8]; |
| 1300 | |
| 1301 | /** Offset 0x0362 - DMI Gen3 Root port preset Tx values per lane |
| 1302 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default |
| 1303 | for each lane |
| 1304 | **/ |
| 1305 | UINT8 DmiGen3DsPortTxPreset[8]; |
| 1306 | |
| 1307 | /** Offset 0x036A - Enable/Disable DMI GEN3 DmiGen3UsPresetEnable |
| 1308 | Enable/Disable DMI GEN3 DmiGen3UsPreset. Auto(0x0)(Default): DmiGen3UsPresetEnable, |
| 1309 | Manual(0x1): Enable DmiGen3UsPresetEnable |
| 1310 | $EN_DIS |
| 1311 | **/ |
| 1312 | UINT8 DmiGen3UsPresetEnable; |
| 1313 | |
| 1314 | /** Offset 0x036B - DMI Gen3 Root port preset Rx values per lane |
| 1315 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default |
| 1316 | for each lane |
| 1317 | **/ |
| 1318 | UINT8 DmiGen3UsPortRxPreset[8]; |
| 1319 | |
| 1320 | /** Offset 0x0373 - DMI Gen3 Root port preset Tx values per lane |
| 1321 | Used for programming DMI Gen3 preset values per lane. Range: 0-10, 7 is default |
| 1322 | for each lane |
| 1323 | **/ |
| 1324 | UINT8 DmiGen3UsPortTxPreset[8]; |
| 1325 | |
| 1326 | /** Offset 0x037B - Reserved |
| 1327 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1328 | UINT8 Reserved23[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1329 | |
| 1330 | /** Offset 0x0383 - Reserved |
| 1331 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1332 | UINT8 Reserved24[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1333 | |
| 1334 | /** Offset 0x038B - Reserved |
| 1335 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1336 | UINT8 Reserved25; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1337 | |
| 1338 | /** Offset 0x038C - Reserved |
| 1339 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1340 | UINT8 Reserved26; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1341 | |
| 1342 | /** Offset 0x038D - Reserved |
| 1343 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1344 | UINT8 Reserved27; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1345 | |
| 1346 | /** Offset 0x038E - Reserved |
| 1347 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1348 | UINT8 Reserved28[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1349 | |
| 1350 | /** Offset 0x0396 - Reserved |
| 1351 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1352 | UINT8 Reserved29; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1353 | |
| 1354 | /** Offset 0x0397 - Reserved |
| 1355 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1356 | UINT8 Reserved30; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1357 | |
| 1358 | /** Offset 0x0398 - Reserved |
| 1359 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1360 | UINT8 Reserved31[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1361 | |
| 1362 | /** Offset 0x03A0 - Reserved |
| 1363 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1364 | UINT8 Reserved32[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1365 | |
| 1366 | /** Offset 0x03A8 - Reserved |
| 1367 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1368 | UINT8 Reserved33; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1369 | |
| 1370 | /** Offset 0x03A9 - Reserved |
| 1371 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1372 | UINT8 Reserved34[8]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1373 | |
| 1374 | /** Offset 0x03B1 - DMI ASPM Control Configuration:{Combo |
| 1375 | Set ASPM Control configuration |
| 1376 | 0:Disabled, 1:L0s, 2:L1, 3:L1L0s |
| 1377 | **/ |
| 1378 | UINT8 DmiAspmCtrl; |
| 1379 | |
| 1380 | /** Offset 0x03B2 - DMI ASPM L1 exit Latency |
| 1381 | Range: 0-7, 4 is default L1 exit Latency |
| 1382 | **/ |
| 1383 | UINT8 DmiAspmL1ExitLatency; |
| 1384 | |
| 1385 | /** Offset 0x03B3 - BIST on Reset |
| 1386 | Enable or Disable BIST on Reset; <b>0: Disable</b>; 1: Enable. |
| 1387 | $EN_DIS |
| 1388 | **/ |
| 1389 | UINT8 BistOnReset; |
| 1390 | |
| 1391 | /** Offset 0x03B4 - Skip Stop PBET Timer Enable/Disable |
| 1392 | Skip Stop PBET Timer; <b>0: Disable</b>; 1: Enable |
| 1393 | $EN_DIS |
| 1394 | **/ |
| 1395 | UINT8 SkipStopPbet; |
| 1396 | |
| 1397 | /** Offset 0x03B5 - C6DRAM power gating feature |
| 1398 | This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM |
| 1399 | power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating |
| 1400 | feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>. |
| 1401 | $EN_DIS |
| 1402 | **/ |
| 1403 | UINT8 EnableC6Dram; |
| 1404 | |
| 1405 | /** Offset 0x03B6 - Over clocking support |
| 1406 | Over clocking support; <b>0: Disable</b>; 1: Enable |
| 1407 | $EN_DIS |
| 1408 | **/ |
| 1409 | UINT8 OcSupport; |
| 1410 | |
| 1411 | /** Offset 0x03B7 - Over clocking Lock |
| 1412 | Over clocking Lock Enable/Disable; 0: Disable; <b>1: Enable</b> |
| 1413 | $EN_DIS |
| 1414 | **/ |
| 1415 | UINT8 OcLock; |
| 1416 | |
| 1417 | /** Offset 0x03B8 - Maximum Core Turbo Ratio Override |
| 1418 | Maximum core turbo ratio override allows to increase CPU core frequency beyond the |
| 1419 | fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 |
| 1420 | **/ |
| 1421 | UINT8 CoreMaxOcRatio; |
| 1422 | |
| 1423 | /** Offset 0x03B9 - Core voltage mode |
| 1424 | Core voltage mode; <b>0: Adaptive</b>; 1: Override. |
| 1425 | $EN_DIS |
| 1426 | **/ |
| 1427 | UINT8 CoreVoltageMode; |
| 1428 | |
| 1429 | /** Offset 0x03BA - Maximum clr turbo ratio override |
| 1430 | Maximum clr turbo ratio override allows to increase CPU clr frequency beyond the |
| 1431 | fused max turbo ratio limit. <b>0: Hardware defaults.</b> Range: 0-85 |
| 1432 | **/ |
| 1433 | UINT8 RingMaxOcRatio; |
| 1434 | |
| 1435 | /** Offset 0x03BB - Hyper Threading Enable/Disable |
| 1436 | Enable or Disable Hyper Threading; 0: Disable; <b>1: Enable</b> |
| 1437 | $EN_DIS |
| 1438 | **/ |
| 1439 | UINT8 HyperThreading; |
| 1440 | |
| 1441 | /** Offset 0x03BC - Enable or Disable CPU Ratio Override |
| 1442 | Enable or Disable CPU Ratio Override; <b>0: Disable</b>; 1: Enable. |
| 1443 | $EN_DIS |
| 1444 | **/ |
| 1445 | UINT8 CpuRatioOverride; |
| 1446 | |
| 1447 | /** Offset 0x03BD - CPU ratio value |
| 1448 | CPU ratio value. Valid Range 0 to 63 |
| 1449 | **/ |
| 1450 | UINT8 CpuRatio; |
| 1451 | |
| 1452 | /** Offset 0x03BE - Boot frequency |
| 1453 | Sets the boot frequency starting from reset vector.- 0: Maximum battery performance. |
| 1454 | 1: Maximum non-turbo performance. <b>2: Turbo performance </b> |
| 1455 | 0:0, 1:1, 2:2 |
| 1456 | **/ |
| 1457 | UINT8 BootFrequency; |
| 1458 | |
| 1459 | /** Offset 0x03BF - Number of active big cores |
| 1460 | Number of active big cores(Depends on Number of big cores). Default 0xFF means to |
| 1461 | active all system supported big cores. <b>0xFF: Active all big cores</b>; 0: Disable |
| 1462 | all big cores; 1: 1; 2: 2; 3: 3; |
| 1463 | 0:Disable all big cores, 1:1, 2:2, 3:3, 0xFF:Active all big cores |
| 1464 | **/ |
| 1465 | UINT8 ActiveCoreCount; |
| 1466 | |
| 1467 | /** Offset 0x03C0 - Processor Early Power On Configuration FCLK setting |
| 1468 | <b>0: 800 MHz (ULT/ULX)</b>. <b>1: 1 GHz (DT/Halo)</b>. Not supported on ULT/ULX.- |
| 1469 | 2: 400 MHz. - 3: Reserved |
| 1470 | 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved |
| 1471 | **/ |
| 1472 | UINT8 FClkFrequency; |
| 1473 | |
| 1474 | /** Offset 0x03C1 - Set JTAG power in C10 and deeper power states |
| 1475 | False: JTAG is power gated in C10 state. True: keeps the JTAG power up during C10 |
| 1476 | and deeper power states for debug purpose. <b>0: False</b>; 1: True. |
| 1477 | 0: False, 1: True |
| 1478 | **/ |
| 1479 | UINT8 JtagC10PowerGateDisable; |
| 1480 | |
| 1481 | /** Offset 0x03C2 - Enable or Disable VMX |
| 1482 | Enable or Disable VMX; 0: Disable; <b>1: Enable</b>. |
| 1483 | $EN_DIS |
| 1484 | **/ |
| 1485 | UINT8 VmxEnable; |
| 1486 | |
| 1487 | /** Offset 0x03C3 - AVX2 Ratio Offset |
| 1488 | 0(Default)= No Offset. Range 0 - 31. Specifies number of bins to decrease AVX ratio |
| 1489 | vs. Core Ratio. Uses Mailbox MSR 0x150, cmd 0x1B. |
| 1490 | **/ |
| 1491 | UINT8 Avx2RatioOffset; |
| 1492 | |
| 1493 | /** Offset 0x03C4 - AVX3 Ratio Offset |
| 1494 | DEPRECATED |
| 1495 | **/ |
| 1496 | UINT8 Avx3RatioOffset; |
| 1497 | |
| 1498 | /** Offset 0x03C5 - BCLK Adaptive Voltage Enable |
| 1499 | When enabled, the CPU V/F curves are aware of BCLK frequency when calculated. </b>0: |
| 1500 | Disable;<b> 1: Enable |
| 1501 | $EN_DIS |
| 1502 | **/ |
| 1503 | UINT8 BclkAdaptiveVoltage; |
| 1504 | |
| 1505 | /** Offset 0x03C6 - core voltage override |
| 1506 | The core voltage override which is applied to the entire range of cpu core frequencies. |
| 1507 | Valid Range 0 to 2000 |
| 1508 | **/ |
| 1509 | UINT16 CoreVoltageOverride; |
| 1510 | |
| 1511 | /** Offset 0x03C8 - Core Turbo voltage Adaptive |
| 1512 | Extra Turbo voltage applied to the cpu core when the cpu is operating in turbo mode. |
| 1513 | Valid Range 0 to 2000 |
| 1514 | **/ |
| 1515 | UINT16 CoreVoltageAdaptive; |
| 1516 | |
| 1517 | /** Offset 0x03CA - Core Turbo voltage Offset |
| 1518 | The voltage offset applied to the core while operating in turbo mode.Valid Range 0 to 1000 |
| 1519 | **/ |
| 1520 | UINT16 CoreVoltageOffset; |
| 1521 | |
| 1522 | /** Offset 0x03CC - Core PLL voltage offset |
| 1523 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 1524 | **/ |
| 1525 | UINT8 CorePllVoltageOffset; |
| 1526 | |
| 1527 | /** Offset 0x03CD - Reserved |
| 1528 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1529 | UINT8 Reserved35; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1530 | |
| 1531 | /** Offset 0x03CE - Ring Downbin |
| 1532 | Ring Downbin enable/disable. When enabled, CPU will ensure the ring ratio is always |
| 1533 | lower than the core ratio.0: Disable; <b>1: Enable.</b> |
| 1534 | $EN_DIS |
| 1535 | **/ |
| 1536 | UINT8 RingDownBin; |
| 1537 | |
| 1538 | /** Offset 0x03CF - Ring voltage mode |
| 1539 | Ring voltage mode; <b>0: Adaptive</b>; 1: Override. |
| 1540 | $EN_DIS |
| 1541 | **/ |
| 1542 | UINT8 RingVoltageMode; |
| 1543 | |
| 1544 | /** Offset 0x03D0 - TjMax Offset |
| 1545 | TjMax offset.Specified value here is clipped by pCode (125 - TjMax Offset) to support |
| 1546 | TjMax in the range of 62 to 115 deg Celsius. Valid Range 10 - 63 |
| 1547 | **/ |
| 1548 | UINT8 TjMaxOffset; |
| 1549 | |
| 1550 | /** Offset 0x03D1 - Reserved |
| 1551 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1552 | UINT8 Reserved36; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1553 | |
| 1554 | /** Offset 0x03D2 - Ring voltage override |
| 1555 | The ring voltage override which is applied to the entire range of cpu ring frequencies. |
| 1556 | Valid Range 0 to 2000 |
| 1557 | **/ |
| 1558 | UINT16 RingVoltageOverride; |
| 1559 | |
| 1560 | /** Offset 0x03D4 - Ring Turbo voltage Adaptive |
| 1561 | Extra Turbo voltage applied to the cpu ring when the cpu is operating in turbo mode. |
| 1562 | Valid Range 0 to 2000 |
| 1563 | **/ |
| 1564 | UINT16 RingVoltageAdaptive; |
| 1565 | |
| 1566 | /** Offset 0x03D6 - Ring Turbo voltage Offset |
| 1567 | The voltage offset applied to the ring while operating in turbo mode. Valid Range 0 to 1000 |
| 1568 | **/ |
| 1569 | UINT16 RingVoltageOffset; |
| 1570 | |
| 1571 | /** Offset 0x03D8 - Enable or Disable TME |
| 1572 | Enable or Disable TME; <b>0: Disable</b>; 1: Enable. |
| 1573 | $EN_DIS |
| 1574 | **/ |
| 1575 | UINT8 TmeEnable; |
| 1576 | |
| 1577 | /** Offset 0x03D9 - Enable CPU CrashLog |
| 1578 | Enable or Disable CPU CrashLog; 0: Disable; <b>1: Enable</b>. |
| 1579 | $EN_DIS |
| 1580 | **/ |
| 1581 | UINT8 CpuCrashLogEnable; |
| 1582 | |
| 1583 | /** Offset 0x03DA - CPU Run Control |
| 1584 | Enable, Disable or Do not configure CPU Run Control; 0: Disable; 1: Enable ; <b>2: |
| 1585 | No Change</b> |
| 1586 | 0:Disabled, 1:Enabled, 2:No Change |
| 1587 | **/ |
| 1588 | UINT8 DebugInterfaceEnable; |
| 1589 | |
| 1590 | /** Offset 0x03DB - CPU Run Control Lock |
| 1591 | Lock or Unlock CPU Run Control; 0: Disable; <b>1: Enable</b>. |
| 1592 | $EN_DIS |
| 1593 | **/ |
| 1594 | UINT8 DebugInterfaceLockEnable; |
| 1595 | |
| 1596 | /** Offset 0x03DC - Reserved |
| 1597 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1598 | UINT8 Reserved37; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1599 | |
| 1600 | /** Offset 0x03DD - Reserved |
| 1601 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1602 | UINT8 Reserved38; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1603 | |
| 1604 | /** Offset 0x03DE - Reserved |
| 1605 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1606 | UINT16 Reserved39; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1607 | |
| 1608 | /** Offset 0x03E0 - Reserved |
| 1609 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1610 | UINT16 Reserved40; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1611 | |
| 1612 | /** Offset 0x03E2 - Reserved |
| 1613 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1614 | UINT16 Reserved41; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1615 | |
| 1616 | /** Offset 0x03E4 - Reserved |
| 1617 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1618 | UINT16 Reserved42[4]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1619 | |
| 1620 | /** Offset 0x03EC - Reserved |
| 1621 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1622 | UINT8 Reserved43[4]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1623 | |
| 1624 | /** Offset 0x03F0 - Reserved |
| 1625 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1626 | UINT8 Reserved44; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1627 | |
| 1628 | /** Offset 0x03F1 - Reserved |
| 1629 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1630 | UINT8 Reserved45; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1631 | |
| 1632 | /** Offset 0x03F2 - Reserved |
| 1633 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1634 | UINT8 Reserved46; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1635 | |
| 1636 | /** Offset 0x03F3 - Reserved |
| 1637 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1638 | UINT8 Reserved47; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1639 | |
| 1640 | /** Offset 0x03F4 - Core VF Point Offset Mode |
| 1641 | Selects Core Voltage & Frequency Offset mode between Legacy and Selection modes. |
| 1642 | In Legacy Mode, setting a global offset for the entire VF curve. In Selection Mode, |
| 1643 | setting a selected VF point; <b>0: Legacy</b>; 1: Selection. |
| 1644 | 0:Legacy, 1:Selection |
| 1645 | **/ |
| 1646 | UINT8 CoreVfPointOffsetMode; |
| 1647 | |
| 1648 | /** Offset 0x03F5 - Reserved |
| 1649 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1650 | UINT8 Reserved48[1]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1651 | |
| 1652 | /** Offset 0x03F6 - Core VF Point Offset |
| 1653 | Array used to specifies the Core Voltage Offset applied to the each selected VF |
| 1654 | Point. This voltage is specified in millivolts. |
| 1655 | **/ |
| 1656 | UINT16 CoreVfPointOffset[15]; |
| 1657 | |
| 1658 | /** Offset 0x0414 - Core VF Point Offset Prefix |
| 1659 | Sets the CoreVfPointOffset value as positive or negative for corresponding core |
| 1660 | VF Point; <b>0: Positive </b>; 1: Negative. |
| 1661 | 0:Positive, 1:Negative |
| 1662 | **/ |
| 1663 | UINT8 CoreVfPointOffsetPrefix[15]; |
| 1664 | |
| 1665 | /** Offset 0x0423 - Core VF Point Ratio |
| 1666 | Array for the each selected Core VF Point to display the ration. |
| 1667 | **/ |
| 1668 | UINT8 CoreVfPointRatio[15]; |
| 1669 | |
| 1670 | /** Offset 0x0432 - Core VF Point Count |
| 1671 | Number of supported Core Voltage & Frequency Point Offset |
| 1672 | **/ |
| 1673 | UINT8 CoreVfPointCount; |
| 1674 | |
| 1675 | /** Offset 0x0433 - Reserved |
| 1676 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1677 | UINT8 Reserved49; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1678 | |
| 1679 | /** Offset 0x0434 - Reserved |
| 1680 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1681 | UINT16 Reserved50[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1682 | |
| 1683 | /** Offset 0x0444 - Reserved |
| 1684 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1685 | UINT8 Reserved51[8]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1686 | |
| 1687 | /** Offset 0x044C - Per Core Max Ratio override |
| 1688 | Enable or disable Per Core PState OC supported by writing OCMB 0x1D to program new |
| 1689 | favored core ratio to each Core. <b>0: Disable</b>, 1: enable |
| 1690 | $EN_DIS |
| 1691 | **/ |
| 1692 | UINT8 PerCoreRatioOverride; |
| 1693 | |
| 1694 | /** Offset 0x044D - Per Core Current Max Ratio |
| 1695 | Array for the Per Core Max Ratio |
| 1696 | **/ |
| 1697 | UINT8 PerCoreRatio[8]; |
| 1698 | |
| 1699 | /** Offset 0x0455 - Reserved |
| 1700 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1701 | UINT8 Reserved52[4]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1702 | |
| 1703 | /** Offset 0x0459 - Reserved |
| 1704 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1705 | UINT8 Reserved53; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1706 | |
| 1707 | /** Offset 0x045A - Pvd Ratio Threshold |
| 1708 | Select PVD Ratio Threshold Value from Range 1 to 40. 0 - Auto/Default. |
| 1709 | **/ |
| 1710 | UINT8 PvdRatioThreshold; |
| 1711 | |
| 1712 | /** Offset 0x045B - Support Unlimited ICCMAX |
| 1713 | DEPRECATED |
| 1714 | $EN_DIS |
| 1715 | **/ |
| 1716 | UINT8 UnlimitedIccMax; |
| 1717 | |
| 1718 | /** Offset 0x045C - Enable CPU CrashLog GPRs dump |
| 1719 | Enable or Disable CPU CrashLog GPRs dump; <b>0: Disable</b>; 1: Enable; 2: Only |
| 1720 | disable Smm GPRs dump |
| 1721 | 0:Disabled, 1:Enabled, 2:Only Smm GPRs Disabled |
| 1722 | **/ |
| 1723 | UINT8 CrashLogGprs; |
| 1724 | |
| 1725 | /** Offset 0x045D - Reserved |
| 1726 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1727 | UINT8 Reserved54; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1728 | |
| 1729 | /** Offset 0x045E - Reserved |
| 1730 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1731 | UINT16 Reserved55[15]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1732 | |
| 1733 | /** Offset 0x047C - Reserved |
| 1734 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1735 | UINT8 Reserved56[15]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1736 | |
| 1737 | /** Offset 0x048B - Reserved |
| 1738 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1739 | UINT8 Reserved57[15]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1740 | |
| 1741 | /** Offset 0x049A - Reserved |
| 1742 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1743 | UINT8 Reserved58; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1744 | |
| 1745 | /** Offset 0x049B - BCLK Frequency Source |
| 1746 | Clock source of BCLK OC frequency, <b>1:CPU BCLK</b>, 2:PCH BCLK, 3:External CLK |
| 1747 | 1:CPU BCLK, 2:PCH BCLK, 3:External CLK |
| 1748 | **/ |
| 1749 | UINT8 BclkSource; |
| 1750 | |
| 1751 | /** Offset 0x049C - GPIO Override |
| 1752 | Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings |
| 1753 | before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO |
| 1754 | configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use |
| 1755 | **/ |
| 1756 | UINT8 GpioOverride; |
| 1757 | |
| 1758 | /** Offset 0x049D - Reserved |
| 1759 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1760 | UINT8 Reserved59[3]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1761 | |
| 1762 | /** Offset 0x04A0 - CPU BCLK OC Frequency |
| 1763 | CPU BCLK OC Frequency in 10KHz units increasing. Value 9800 (10KHz) = 98MHz <b>0 |
| 1764 | - Auto</b>. Range is 8000-50000 (10KHz). |
| 1765 | **/ |
| 1766 | UINT32 CpuBclkOcFrequency; |
| 1767 | |
| 1768 | /** Offset 0x04A4 - Reserved |
| 1769 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1770 | UINT32 Reserved60; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1771 | |
| 1772 | /** Offset 0x04A8 - Reserved |
| 1773 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1774 | UINT32 Reserved61; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1775 | |
| 1776 | /** Offset 0x04AC - Reserved |
| 1777 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1778 | UINT8 Reserved62; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1779 | |
| 1780 | /** Offset 0x04AD - Reserved |
| 1781 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1782 | UINT8 Reserved63; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1783 | |
| 1784 | /** Offset 0x04AE - Reserved |
| 1785 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1786 | UINT8 Reserved64; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1787 | |
| 1788 | /** Offset 0x04AF - Reserved |
| 1789 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1790 | UINT8 Reserved65; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1791 | |
| 1792 | /** Offset 0x04B0 - Reserved |
| 1793 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1794 | UINT16 Reserved66; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1795 | |
| 1796 | /** Offset 0x04B2 - Reserved |
| 1797 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1798 | UINT8 Reserved67; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1799 | |
| 1800 | /** Offset 0x04B3 - Reserved |
| 1801 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1802 | UINT8 Reserved68; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1803 | |
| 1804 | /** Offset 0x04B4 - Reserved |
| 1805 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1806 | UINT16 Reserved69; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1807 | |
| 1808 | /** Offset 0x04B6 - Reserved |
| 1809 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1810 | UINT8 Reserved70; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1811 | |
| 1812 | /** Offset 0x04B7 - Reserved |
| 1813 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1814 | UINT8 Reserved71; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1815 | |
| 1816 | /** Offset 0x04B8 - Reserved |
| 1817 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1818 | UINT8 Reserved72; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1819 | |
| 1820 | /** Offset 0x04B9 - Reserved |
| 1821 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1822 | UINT8 Reserved73; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1823 | |
| 1824 | /** Offset 0x04BA - Reserved |
| 1825 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1826 | UINT8 Reserved74; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1827 | |
| 1828 | /** Offset 0x04BB - Reserved |
| 1829 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1830 | UINT8 Reserved75; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1831 | |
| 1832 | /** Offset 0x04BC - Reserved |
| 1833 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1834 | UINT8 Reserved76; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1835 | |
| 1836 | /** Offset 0x04BD - Reserved |
| 1837 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1838 | UINT8 Reserved77[3]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1839 | |
| 1840 | /** Offset 0x04C0 - Reserved |
| 1841 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1842 | UINT32 Reserved78; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1843 | |
| 1844 | /** Offset 0x04C4 - Reserved |
| 1845 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1846 | UINT8 Reserved79; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1847 | |
| 1848 | /** Offset 0x04C5 - Reserved |
| 1849 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1850 | UINT8 Reserved80; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 1851 | |
| 1852 | /** Offset 0x04C6 - Reserved |
| 1853 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1854 | UINT8 Reserved81[6]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1855 | |
| 1856 | /** Offset 0x04CC - BiosGuard |
| 1857 | Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable |
| 1858 | $EN_DIS |
| 1859 | **/ |
| 1860 | UINT8 BiosGuard; |
| 1861 | |
| 1862 | /** Offset 0x04CD |
| 1863 | **/ |
| 1864 | UINT8 BiosGuardToolsInterface; |
| 1865 | |
| 1866 | /** Offset 0x04CE - Txt |
| 1867 | Enable/Disable. 0: Disable, Enable/Disable Txt feature, 1: enable |
| 1868 | $EN_DIS |
| 1869 | **/ |
| 1870 | UINT8 Txt; |
| 1871 | |
| 1872 | /** Offset 0x04CF - Reserved |
| 1873 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1874 | UINT8 Reserved82; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1875 | |
| 1876 | /** Offset 0x04D0 - PrmrrSize |
| 1877 | Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable |
| 1878 | **/ |
| 1879 | UINT32 PrmrrSize; |
| 1880 | |
| 1881 | /** Offset 0x04D4 - SinitMemorySize |
| 1882 | Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable |
| 1883 | **/ |
| 1884 | UINT32 SinitMemorySize; |
| 1885 | |
| 1886 | /** Offset 0x04D8 - TxtDprMemoryBase |
| 1887 | Enable/Disable. 0: Disable, define default value of TxtDprMemoryBase , 1: enable |
| 1888 | **/ |
| 1889 | UINT64 TxtDprMemoryBase; |
| 1890 | |
| 1891 | /** Offset 0x04E0 - TxtHeapMemorySize |
| 1892 | Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable |
| 1893 | **/ |
| 1894 | UINT32 TxtHeapMemorySize; |
| 1895 | |
| 1896 | /** Offset 0x04E4 - TxtDprMemorySize |
| 1897 | Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable |
| 1898 | **/ |
| 1899 | UINT32 TxtDprMemorySize; |
| 1900 | |
| 1901 | /** Offset 0x04E8 - BiosAcmBase |
| 1902 | Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable |
| 1903 | **/ |
| 1904 | UINT32 BiosAcmBase; |
| 1905 | |
| 1906 | /** Offset 0x04EC - BiosAcmSize |
| 1907 | Enable/Disable. 0: Disable, define default value of BiosAcmSize , 1: enable |
| 1908 | **/ |
| 1909 | UINT32 BiosAcmSize; |
| 1910 | |
| 1911 | /** Offset 0x04F0 - ApStartupBase |
| 1912 | Enable/Disable. 0: Disable, define default value of BiosAcmBase , 1: enable |
| 1913 | **/ |
| 1914 | UINT32 ApStartupBase; |
| 1915 | |
| 1916 | /** Offset 0x04F4 - TgaSize |
| 1917 | Enable/Disable. 0: Disable, define default value of TgaSize , 1: enable |
| 1918 | **/ |
| 1919 | UINT32 TgaSize; |
| 1920 | |
| 1921 | /** Offset 0x04F8 - TxtLcpPdBase |
| 1922 | Enable/Disable. 0: Disable, define default value of TxtLcpPdBase , 1: enable |
| 1923 | **/ |
| 1924 | UINT64 TxtLcpPdBase; |
| 1925 | |
| 1926 | /** Offset 0x0500 - TxtLcpPdSize |
| 1927 | Enable/Disable. 0: Disable, define default value of TxtLcpPdSize , 1: enable |
| 1928 | **/ |
| 1929 | UINT64 TxtLcpPdSize; |
| 1930 | |
| 1931 | /** Offset 0x0508 - IsTPMPresence |
| 1932 | IsTPMPresence default values |
| 1933 | **/ |
| 1934 | UINT8 IsTPMPresence; |
| 1935 | |
| 1936 | /** Offset 0x0509 - Reserved |
| 1937 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 1938 | UINT8 Reserved83[32]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 1939 | |
| 1940 | /** Offset 0x0529 - Enable PCH HSIO PCIE Rx Set Ctle |
| 1941 | Enable PCH PCIe Gen 3 Set CTLE Value. |
| 1942 | **/ |
| 1943 | UINT8 PchPcieHsioRxSetCtleEnable[28]; |
| 1944 | |
| 1945 | /** Offset 0x0545 - PCH HSIO PCIE Rx Set Ctle Value |
| 1946 | PCH PCIe Gen 3 Set CTLE Value. |
| 1947 | **/ |
| 1948 | UINT8 PchPcieHsioRxSetCtle[28]; |
| 1949 | |
| 1950 | /** Offset 0x0561 - Enble PCH HSIO PCIE TX Gen 1 Downscale Amplitude Adjustment value override |
| 1951 | 0: Disable; 1: Enable. |
| 1952 | **/ |
| 1953 | UINT8 PchPcieHsioTxGen1DownscaleAmpEnable[28]; |
| 1954 | |
| 1955 | /** Offset 0x057D - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value |
| 1956 | PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. |
| 1957 | **/ |
| 1958 | UINT8 PchPcieHsioTxGen1DownscaleAmp[28]; |
| 1959 | |
| 1960 | /** Offset 0x0599 - Enable PCH HSIO PCIE TX Gen 2 Downscale Amplitude Adjustment value override |
| 1961 | 0: Disable; 1: Enable. |
| 1962 | **/ |
| 1963 | UINT8 PchPcieHsioTxGen2DownscaleAmpEnable[28]; |
| 1964 | |
| 1965 | /** Offset 0x05B5 - PCH HSIO PCIE Gen 2 TX Output Downscale Amplitude Adjustment value |
| 1966 | PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value. |
| 1967 | **/ |
| 1968 | UINT8 PchPcieHsioTxGen2DownscaleAmp[28]; |
| 1969 | |
| 1970 | /** Offset 0x05D1 - Enable PCH HSIO PCIE TX Gen 3 Downscale Amplitude Adjustment value override |
| 1971 | 0: Disable; 1: Enable. |
| 1972 | **/ |
| 1973 | UINT8 PchPcieHsioTxGen3DownscaleAmpEnable[28]; |
| 1974 | |
| 1975 | /** Offset 0x05ED - PCH HSIO PCIE Gen 3 TX Output Downscale Amplitude Adjustment value |
| 1976 | PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value. |
| 1977 | **/ |
| 1978 | UINT8 PchPcieHsioTxGen3DownscaleAmp[28]; |
| 1979 | |
| 1980 | /** Offset 0x0609 - Enable PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment Setting value override |
| 1981 | 0: Disable; 1: Enable. |
| 1982 | **/ |
| 1983 | UINT8 PchPcieHsioTxGen1DeEmphEnable[28]; |
| 1984 | |
| 1985 | /** Offset 0x0625 - PCH HSIO PCIE Gen 1 TX Output De-Emphasis Adjustment value |
| 1986 | PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting. |
| 1987 | **/ |
| 1988 | UINT8 PchPcieHsioTxGen1DeEmph[28]; |
| 1989 | |
| 1990 | /** Offset 0x0641 - Enable PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting value override |
| 1991 | 0: Disable; 1: Enable. |
| 1992 | **/ |
| 1993 | UINT8 PchPcieHsioTxGen2DeEmph3p5Enable[28]; |
| 1994 | |
| 1995 | /** Offset 0x065D - PCH HSIO PCIE Gen 2 TX Output -3.5dB De-Emphasis Adjustment value |
| 1996 | PCH PCIe Gen 2 TX Output -3.5dB De-Emphasis Adjustment Setting. |
| 1997 | **/ |
| 1998 | UINT8 PchPcieHsioTxGen2DeEmph3p5[28]; |
| 1999 | |
| 2000 | /** Offset 0x0679 - Enable PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting value override |
| 2001 | 0: Disable; 1: Enable. |
| 2002 | **/ |
| 2003 | UINT8 PchPcieHsioTxGen2DeEmph6p0Enable[28]; |
| 2004 | |
| 2005 | /** Offset 0x0695 - PCH HSIO PCIE Gen 2 TX Output -6.0dB De-Emphasis Adjustment value |
| 2006 | PCH PCIe Gen 2 TX Output -6.0dB De-Emphasis Adjustment Setting. |
| 2007 | **/ |
| 2008 | UINT8 PchPcieHsioTxGen2DeEmph6p0[28]; |
| 2009 | |
| 2010 | /** Offset 0x06B1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override |
| 2011 | 0: Disable; 1: Enable. |
| 2012 | **/ |
| 2013 | UINT8 PchSataHsioRxGen1EqBoostMagEnable[8]; |
| 2014 | |
| 2015 | /** Offset 0x06B9 - PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value |
| 2016 | PCH HSIO SATA 1.5 Gb/s Receiver Equalization Boost Magnitude Adjustment value. |
| 2017 | **/ |
| 2018 | UINT8 PchSataHsioRxGen1EqBoostMag[8]; |
| 2019 | |
| 2020 | /** Offset 0x06C1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override |
| 2021 | 0: Disable; 1: Enable. |
| 2022 | **/ |
| 2023 | UINT8 PchSataHsioRxGen2EqBoostMagEnable[8]; |
| 2024 | |
| 2025 | /** Offset 0x06C9 - PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value |
| 2026 | PCH HSIO SATA 3.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. |
| 2027 | **/ |
| 2028 | UINT8 PchSataHsioRxGen2EqBoostMag[8]; |
| 2029 | |
| 2030 | /** Offset 0x06D1 - Enable PCH HSIO SATA Receiver Equalization Boost Magnitude Adjustment Value override |
| 2031 | 0: Disable; 1: Enable. |
| 2032 | **/ |
| 2033 | UINT8 PchSataHsioRxGen3EqBoostMagEnable[8]; |
| 2034 | |
| 2035 | /** Offset 0x06D9 - PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value |
| 2036 | PCH HSIO SATA 6.0 Gb/s Receiver Equalization Boost Magnitude Adjustment value. |
| 2037 | **/ |
| 2038 | UINT8 PchSataHsioRxGen3EqBoostMag[8]; |
| 2039 | |
| 2040 | /** Offset 0x06E1 - Enable PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override |
| 2041 | 0: Disable; 1: Enable. |
| 2042 | **/ |
| 2043 | UINT8 PchSataHsioTxGen1DownscaleAmpEnable[8]; |
| 2044 | |
| 2045 | /** Offset 0x06E9 - PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value |
| 2046 | PCH HSIO SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value. |
| 2047 | **/ |
| 2048 | UINT8 PchSataHsioTxGen1DownscaleAmp[8]; |
| 2049 | |
| 2050 | /** Offset 0x06F1 - Enable PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override |
| 2051 | 0: Disable; 1: Enable. |
| 2052 | **/ |
| 2053 | UINT8 PchSataHsioTxGen2DownscaleAmpEnable[8]; |
| 2054 | |
| 2055 | /** Offset 0x06F9 - PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value |
| 2056 | PCH HSIO SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value. |
| 2057 | **/ |
| 2058 | UINT8 PchSataHsioTxGen2DownscaleAmp[8]; |
| 2059 | |
| 2060 | /** Offset 0x0701 - Enable PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override |
| 2061 | 0: Disable; 1: Enable. |
| 2062 | **/ |
| 2063 | UINT8 PchSataHsioTxGen3DownscaleAmpEnable[8]; |
| 2064 | |
| 2065 | /** Offset 0x0709 - PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value |
| 2066 | PCH HSIO SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value. |
| 2067 | **/ |
| 2068 | UINT8 PchSataHsioTxGen3DownscaleAmp[8]; |
| 2069 | |
| 2070 | /** Offset 0x0711 - Enable PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override |
| 2071 | 0: Disable; 1: Enable. |
| 2072 | **/ |
| 2073 | UINT8 PchSataHsioTxGen1DeEmphEnable[8]; |
| 2074 | |
| 2075 | /** Offset 0x0719 - PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting |
| 2076 | PCH HSIO SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting. |
| 2077 | **/ |
| 2078 | UINT8 PchSataHsioTxGen1DeEmph[8]; |
| 2079 | |
| 2080 | /** Offset 0x0721 - Enable PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override |
| 2081 | 0: Disable; 1: Enable. |
| 2082 | **/ |
| 2083 | UINT8 PchSataHsioTxGen2DeEmphEnable[8]; |
| 2084 | |
| 2085 | /** Offset 0x0729 - PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting |
| 2086 | PCH HSIO SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting. |
| 2087 | **/ |
| 2088 | UINT8 PchSataHsioTxGen2DeEmph[8]; |
| 2089 | |
| 2090 | /** Offset 0x0731 - Enable PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override |
| 2091 | 0: Disable; 1: Enable. |
| 2092 | **/ |
| 2093 | UINT8 PchSataHsioTxGen3DeEmphEnable[8]; |
| 2094 | |
| 2095 | /** Offset 0x0739 - PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting |
| 2096 | PCH HSIO SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting. |
| 2097 | **/ |
| 2098 | UINT8 PchSataHsioTxGen3DeEmph[8]; |
| 2099 | |
| 2100 | /** Offset 0x0741 - PCH LPC Enhanced Port 80 Decoding |
| 2101 | Original LPC only decodes one byte of port 80h. |
| 2102 | $EN_DIS |
| 2103 | **/ |
| 2104 | UINT8 PchLpcEnhancePort8xhDecoding; |
| 2105 | |
| 2106 | /** Offset 0x0742 - PCH Port80 Route |
| 2107 | Control where the Port 80h cycles are sent, 0: LPC; 1: PCI. |
| 2108 | 0:LPC, 1:PCI |
| 2109 | **/ |
| 2110 | UINT8 PchPort80Route; |
| 2111 | |
Bora Guvendik | 225e79b | 2022-05-31 10:51:17 -0700 | [diff] [blame] | 2112 | /** Offset 0x0743 - Enable SMBus ARP support |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2113 | Enable SMBus ARP support. |
| 2114 | $EN_DIS |
| 2115 | **/ |
| 2116 | UINT8 SmbusArpEnable; |
| 2117 | |
Bora Guvendik | 225e79b | 2022-05-31 10:51:17 -0700 | [diff] [blame] | 2118 | /** Offset 0x0744 - Number of RsvdSmbusAddressTable. |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2119 | The number of elements in the RsvdSmbusAddressTable. |
| 2120 | **/ |
| 2121 | UINT8 PchNumRsvdSmbusAddresses; |
| 2122 | |
Bora Guvendik | 225e79b | 2022-05-31 10:51:17 -0700 | [diff] [blame] | 2123 | /** Offset 0x0745 - Reserved |
| 2124 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2125 | UINT8 Reserved84; |
Bora Guvendik | 225e79b | 2022-05-31 10:51:17 -0700 | [diff] [blame] | 2126 | |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2127 | /** Offset 0x0746 - SMBUS Base Address |
| 2128 | SMBUS Base Address (IO space). |
| 2129 | **/ |
| 2130 | UINT16 PchSmbusIoBase; |
| 2131 | |
| 2132 | /** Offset 0x0748 - Enable SMBus Alert Pin |
| 2133 | Enable SMBus Alert Pin. |
| 2134 | $EN_DIS |
| 2135 | **/ |
| 2136 | UINT8 PchSmbAlertEnable; |
| 2137 | |
| 2138 | /** Offset 0x0749 - Usage type for ClkSrc |
| 2139 | 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use |
| 2140 | (free running), 0xFF: not used |
| 2141 | **/ |
| 2142 | UINT8 PcieClkSrcUsage[18]; |
| 2143 | |
| 2144 | /** Offset 0x075B - Reserved |
| 2145 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2146 | UINT8 Reserved85[14]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2147 | |
| 2148 | /** Offset 0x0769 - ClkReq-to-ClkSrc mapping |
| 2149 | Number of ClkReq signal assigned to ClkSrc |
| 2150 | **/ |
| 2151 | UINT8 PcieClkSrcClkReq[18]; |
| 2152 | |
| 2153 | /** Offset 0x077B - Reserved |
| 2154 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2155 | UINT8 Reserved86[14]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 2156 | |
| 2157 | /** Offset 0x0789 - Reserved |
| 2158 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2159 | UINT8 Reserved87[3]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 2160 | |
| 2161 | /** Offset 0x078C - Reserved |
| 2162 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2163 | UINT32 Reserved88[18]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 2164 | |
| 2165 | /** Offset 0x07D4 - Reserved |
| 2166 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2167 | UINT32 Reserved89; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2168 | |
| 2169 | /** Offset 0x07D8 - Enable PCIE RP Mask |
| 2170 | Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 |
| 2171 | for port1, bit1 for port2, and so on. |
| 2172 | **/ |
| 2173 | UINT32 PcieRpEnableMask; |
| 2174 | |
| 2175 | /** Offset 0x07DC - VC Type |
| 2176 | Virtual Channel Type Select: 0: VC0, 1: VC1. |
| 2177 | 0: VC0, 1: VC1 |
| 2178 | **/ |
| 2179 | UINT8 PchHdaVcType; |
| 2180 | |
| 2181 | /** Offset 0x07DD - Universal Audio Architecture compliance for DSP enabled system |
| 2182 | 0: Not-UAA Compliant (Intel SST driver supported only), 1: UAA Compliant (HDA Inbox |
| 2183 | driver or SST driver supported). |
| 2184 | $EN_DIS |
| 2185 | **/ |
| 2186 | UINT8 PchHdaDspUaaCompliance; |
| 2187 | |
| 2188 | /** Offset 0x07DE - Enable HD Audio Link |
| 2189 | Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. |
| 2190 | $EN_DIS |
| 2191 | **/ |
| 2192 | UINT8 PchHdaAudioLinkHdaEnable; |
| 2193 | |
| 2194 | /** Offset 0x07DF - Enable HDA SDI lanes |
| 2195 | Enable/disable HDA SDI lanes. |
| 2196 | **/ |
| 2197 | UINT8 PchHdaSdiEnable[2]; |
| 2198 | |
| 2199 | /** Offset 0x07E1 - HDA Power/Clock Gating (PGD/CGD) |
| 2200 | Enable/Disable HD Audio Power and Clock Gating(POR: Enable). 0: PLATFORM_POR, 1: |
| 2201 | FORCE_ENABLE, 2: FORCE_DISABLE. |
| 2202 | 0: POR, 1: Force Enable, 2: Force Disable |
| 2203 | **/ |
| 2204 | UINT8 PchHdaTestPowerClockGating; |
| 2205 | |
| 2206 | /** Offset 0x07E2 - Enable HD Audio DMIC_N Link |
| 2207 | Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. |
| 2208 | **/ |
| 2209 | UINT8 PchHdaAudioLinkDmicEnable[2]; |
| 2210 | |
| 2211 | /** Offset 0x07E4 - DMIC<N> ClkA Pin Muxing (N - DMIC number) |
| 2212 | Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKA_* |
| 2213 | **/ |
| 2214 | UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; |
| 2215 | |
| 2216 | /** Offset 0x07EC - DMIC<N> ClkB Pin Muxing |
| 2217 | Determines DMIC<N> ClkA Pin muxing. See GPIO_*_MUXING_DMIC<N>_CLKB_* |
| 2218 | **/ |
| 2219 | UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; |
| 2220 | |
| 2221 | /** Offset 0x07F4 - Enable HD Audio DSP |
| 2222 | Enable/disable HD Audio DSP feature. |
| 2223 | $EN_DIS |
| 2224 | **/ |
| 2225 | UINT8 PchHdaDspEnable; |
| 2226 | |
| 2227 | /** Offset 0x07F5 - Reserved |
| 2228 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2229 | UINT8 Reserved90[3]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2230 | |
| 2231 | /** Offset 0x07F8 - DMIC<N> Data Pin Muxing |
| 2232 | Determines DMIC<N> Data Pin muxing. See GPIO_*_MUXING_DMIC<N>_DATA_* |
| 2233 | **/ |
| 2234 | UINT32 PchHdaAudioLinkDmicDataPinMux[2]; |
| 2235 | |
| 2236 | /** Offset 0x0800 - Enable HD Audio SSP0 Link |
| 2237 | Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 |
| 2238 | **/ |
| 2239 | UINT8 PchHdaAudioLinkSspEnable[6]; |
| 2240 | |
| 2241 | /** Offset 0x0806 - Enable HD Audio SoundWire#N Link |
| 2242 | Enable/disable HD Audio SNDW#N link. Muxed with HDA. |
| 2243 | **/ |
| 2244 | UINT8 PchHdaAudioLinkSndwEnable[4]; |
| 2245 | |
| 2246 | /** Offset 0x080A - iDisp-Link Frequency |
| 2247 | iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. |
| 2248 | 4: 96MHz, 3: 48MHz |
| 2249 | **/ |
| 2250 | UINT8 PchHdaIDispLinkFrequency; |
| 2251 | |
| 2252 | /** Offset 0x080B - iDisp-Link T-mode |
| 2253 | iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| 2254 | 0: 2T, 2: 4T, 3: 8T, 4: 16T |
| 2255 | **/ |
| 2256 | UINT8 PchHdaIDispLinkTmode; |
| 2257 | |
| 2258 | /** Offset 0x080C - iDisplay Audio Codec disconnection |
| 2259 | 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. |
| 2260 | $EN_DIS |
| 2261 | **/ |
| 2262 | UINT8 PchHdaIDispCodecDisconnect; |
| 2263 | |
| 2264 | /** Offset 0x080D - CNVi DDR RFI Mitigation |
| 2265 | Enable/Disable DDR RFI Mitigation. Default is ENABLE. 0: DISABLE, 1: ENABLE |
| 2266 | $EN_DIS |
| 2267 | **/ |
| 2268 | UINT8 CnviDdrRfim; |
| 2269 | |
| 2270 | /** Offset 0x080E - Debug Interfaces |
| 2271 | Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, |
| 2272 | BIT2 - Not used. |
| 2273 | **/ |
| 2274 | UINT8 PcdDebugInterfaceFlags; |
| 2275 | |
| 2276 | /** Offset 0x080F - Serial Io Uart Debug Controller Number |
| 2277 | Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT |
| 2278 | Core interface, it cannot be used for debug purpose. |
| 2279 | 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 |
| 2280 | **/ |
| 2281 | UINT8 SerialIoUartDebugControllerNumber; |
| 2282 | |
| 2283 | /** Offset 0x0810 - Serial Io Uart Debug Auto Flow |
| 2284 | Enables UART hardware flow control, CTS and RTS lines. |
| 2285 | $EN_DIS |
| 2286 | **/ |
| 2287 | UINT8 SerialIoUartDebugAutoFlow; |
| 2288 | |
| 2289 | /** Offset 0x0811 - Reserved |
| 2290 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2291 | UINT8 Reserved91[3]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2292 | |
| 2293 | /** Offset 0x0814 - Serial Io Uart Debug BaudRate |
| 2294 | Set default BaudRate Supported from 0 - default to 6000000. Recommended values 9600, |
| 2295 | 19200, 57600, 115200, 460800, 921600, 1500000, 1843200, 3000000, 3686400, 6000000 |
| 2296 | **/ |
| 2297 | UINT32 SerialIoUartDebugBaudRate; |
| 2298 | |
| 2299 | /** Offset 0x0818 - Serial Io Uart Debug Parity |
| 2300 | Set default Parity. |
| 2301 | 0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity |
| 2302 | **/ |
| 2303 | UINT8 SerialIoUartDebugParity; |
| 2304 | |
| 2305 | /** Offset 0x0819 - Serial Io Uart Debug Stop Bits |
| 2306 | Set default stop bits. |
| 2307 | 0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits |
| 2308 | **/ |
| 2309 | UINT8 SerialIoUartDebugStopBits; |
| 2310 | |
| 2311 | /** Offset 0x081A - Serial Io Uart Debug Data Bits |
| 2312 | Set default word length. 0: Default, 5,6,7,8 |
| 2313 | 5:5BITS, 6:6BITS, 7:7BITS, 8:8BITS |
| 2314 | **/ |
| 2315 | UINT8 SerialIoUartDebugDataBits; |
| 2316 | |
| 2317 | /** Offset 0x081B - Reserved |
| 2318 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2319 | UINT8 Reserved92; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2320 | |
| 2321 | /** Offset 0x081C - Serial Io Uart Debug Mmio Base |
| 2322 | Select SerialIo Uart default MMIO resource in SEC/PEI phase when PcdSerialIoUartMode |
| 2323 | = SerialIoUartPci. |
| 2324 | **/ |
| 2325 | UINT32 SerialIoUartDebugMmioBase; |
| 2326 | |
| 2327 | /** Offset 0x0820 - ISA Serial Base selection |
| 2328 | Select ISA Serial Base address. Default is 0x3F8. |
| 2329 | 0:0x3F8, 1:0x2F8 |
| 2330 | **/ |
| 2331 | UINT8 PcdIsaSerialUartBase; |
| 2332 | |
| 2333 | /** Offset 0x0821 - GT PLL voltage offset |
| 2334 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 2335 | **/ |
| 2336 | UINT8 GtPllVoltageOffset; |
| 2337 | |
| 2338 | /** Offset 0x0822 - Ring PLL voltage offset |
| 2339 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 2340 | **/ |
| 2341 | UINT8 RingPllVoltageOffset; |
| 2342 | |
| 2343 | /** Offset 0x0823 - System Agent PLL voltage offset |
| 2344 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 2345 | **/ |
| 2346 | UINT8 SaPllVoltageOffset; |
| 2347 | |
| 2348 | /** Offset 0x0824 - Memory Controller PLL voltage offset |
| 2349 | Core PLL voltage offset. <b>0: No offset</b>. Range 0-15 |
| 2350 | **/ |
| 2351 | UINT8 McPllVoltageOffset; |
| 2352 | |
| 2353 | /** Offset 0x0825 - MRC Safe Config |
| 2354 | Enables/Disable MRC Safe Config |
| 2355 | $EN_DIS |
| 2356 | **/ |
| 2357 | UINT8 MrcSafeConfig; |
| 2358 | |
| 2359 | /** Offset 0x0826 - TCSS Thunderbolt PCIE Root Port 0 Enable |
| 2360 | Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled |
| 2361 | $EN_DIS |
| 2362 | **/ |
| 2363 | UINT8 TcssItbtPcie0En; |
| 2364 | |
| 2365 | /** Offset 0x0827 - TCSS Thunderbolt PCIE Root Port 1 Enable |
| 2366 | Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled |
| 2367 | $EN_DIS |
| 2368 | **/ |
| 2369 | UINT8 TcssItbtPcie1En; |
| 2370 | |
| 2371 | /** Offset 0x0828 - TCSS Thunderbolt PCIE Root Port 2 Enable |
| 2372 | Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled |
| 2373 | $EN_DIS |
| 2374 | **/ |
| 2375 | UINT8 TcssItbtPcie2En; |
| 2376 | |
| 2377 | /** Offset 0x0829 - TCSS Thunderbolt PCIE Root Port 3 Enable |
| 2378 | Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled |
| 2379 | $EN_DIS |
| 2380 | **/ |
| 2381 | UINT8 TcssItbtPcie3En; |
| 2382 | |
| 2383 | /** Offset 0x082A - TCSS USB HOST (xHCI) Enable |
| 2384 | Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below |
| 2385 | $EN_DIS |
| 2386 | **/ |
| 2387 | UINT8 TcssXhciEn; |
| 2388 | |
| 2389 | /** Offset 0x082B - TCSS USB DEVICE (xDCI) Enable |
| 2390 | Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled |
| 2391 | $EN_DIS |
| 2392 | **/ |
| 2393 | UINT8 TcssXdciEn; |
| 2394 | |
| 2395 | /** Offset 0x082C - TCSS DMA0 Enable |
| 2396 | Set TCSS DMA0. 0:Disabled 1:Enabled |
| 2397 | $EN_DIS |
| 2398 | **/ |
| 2399 | UINT8 TcssDma0En; |
| 2400 | |
| 2401 | /** Offset 0x082D - TCSS DMA1 Enable |
| 2402 | Set TCSS DMA1. 0:Disabled 1:Enabled |
| 2403 | $EN_DIS |
| 2404 | **/ |
| 2405 | UINT8 TcssDma1En; |
| 2406 | |
| 2407 | /** Offset 0x082E - PcdSerialDebugBaudRate |
| 2408 | Baud Rate for Serial Debug Messages. 3:9600, 4:19200, 6:56700, 7:115200. |
| 2409 | 3:9600, 4:19200, 6:56700, 7:115200 |
| 2410 | **/ |
| 2411 | UINT8 PcdSerialDebugBaudRate; |
| 2412 | |
| 2413 | /** Offset 0x082F - HobBufferSize |
| 2414 | Size to set HOB Buffer. 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value(assuming 63KB |
| 2415 | total HOB size). |
| 2416 | 0:Default, 1: 1 Byte, 2: 1 KB, 3: Max value |
| 2417 | **/ |
| 2418 | UINT8 HobBufferSize; |
| 2419 | |
| 2420 | /** Offset 0x0830 - Early Command Training |
| 2421 | Enables/Disable Early Command Training |
| 2422 | $EN_DIS |
| 2423 | **/ |
| 2424 | UINT8 ECT; |
| 2425 | |
| 2426 | /** Offset 0x0831 - SenseAmp Offset Training |
| 2427 | Enables/Disable SenseAmp Offset Training |
| 2428 | $EN_DIS |
| 2429 | **/ |
| 2430 | UINT8 SOT; |
| 2431 | |
| 2432 | /** Offset 0x0832 - Early ReadMPR Timing Centering 2D |
| 2433 | Enables/Disable Early ReadMPR Timing Centering 2D |
| 2434 | $EN_DIS |
| 2435 | **/ |
| 2436 | UINT8 ERDMPRTC2D; |
| 2437 | |
| 2438 | /** Offset 0x0833 - Read MPR Training |
| 2439 | Enables/Disable Read MPR Training |
| 2440 | $EN_DIS |
| 2441 | **/ |
| 2442 | UINT8 RDMPRT; |
| 2443 | |
| 2444 | /** Offset 0x0834 - Receive Enable Training |
| 2445 | Enables/Disable Receive Enable Training |
| 2446 | $EN_DIS |
| 2447 | **/ |
| 2448 | UINT8 RCVET; |
| 2449 | |
| 2450 | /** Offset 0x0835 - Jedec Write Leveling |
| 2451 | Enables/Disable Jedec Write Leveling |
| 2452 | $EN_DIS |
| 2453 | **/ |
| 2454 | UINT8 JWRL; |
| 2455 | |
| 2456 | /** Offset 0x0836 - Early Write Time Centering 2D |
| 2457 | Enables/Disable Early Write Time Centering 2D |
| 2458 | $EN_DIS |
| 2459 | **/ |
| 2460 | UINT8 EWRTC2D; |
| 2461 | |
| 2462 | /** Offset 0x0837 - Early Read Time Centering 2D |
| 2463 | Enables/Disable Early Read Time Centering 2D |
| 2464 | $EN_DIS |
| 2465 | **/ |
| 2466 | UINT8 ERDTC2D; |
| 2467 | |
| 2468 | /** Offset 0x0838 - Write Timing Centering 1D |
| 2469 | Enables/Disable Write Timing Centering 1D |
| 2470 | $EN_DIS |
| 2471 | **/ |
| 2472 | UINT8 WRTC1D; |
| 2473 | |
| 2474 | /** Offset 0x0839 - Write Voltage Centering 1D |
| 2475 | Enables/Disable Write Voltage Centering 1D |
| 2476 | $EN_DIS |
| 2477 | **/ |
| 2478 | UINT8 WRVC1D; |
| 2479 | |
| 2480 | /** Offset 0x083A - Read Timing Centering 1D |
| 2481 | Enables/Disable Read Timing Centering 1D |
| 2482 | $EN_DIS |
| 2483 | **/ |
| 2484 | UINT8 RDTC1D; |
| 2485 | |
| 2486 | /** Offset 0x083B - Dimm ODT Training |
| 2487 | Enables/Disable Dimm ODT Training |
| 2488 | $EN_DIS |
| 2489 | **/ |
| 2490 | UINT8 DIMMODTT; |
| 2491 | |
| 2492 | /** Offset 0x083C - DIMM RON Training |
| 2493 | Enables/Disable DIMM RON Training |
| 2494 | $EN_DIS |
| 2495 | **/ |
| 2496 | UINT8 DIMMRONT; |
| 2497 | |
| 2498 | /** Offset 0x083D - Write Drive Strength/Equalization 2D |
| 2499 | Enables/Disable Write Drive Strength/Equalization 2D |
| 2500 | $EN_DIS |
| 2501 | **/ |
| 2502 | UINT8 WRDSEQT; |
| 2503 | |
| 2504 | /** Offset 0x083E - Write Slew Rate Training |
| 2505 | Enables/Disable Write Slew Rate Training |
| 2506 | $EN_DIS |
| 2507 | **/ |
| 2508 | UINT8 WRSRT; |
| 2509 | |
| 2510 | /** Offset 0x083F - Read ODT Training |
| 2511 | Enables/Disable Read ODT Training |
| 2512 | $EN_DIS |
| 2513 | **/ |
| 2514 | UINT8 RDODTT; |
| 2515 | |
| 2516 | /** Offset 0x0840 - Read Equalization Training |
| 2517 | Enables/Disable Read Equalization Training |
| 2518 | $EN_DIS |
| 2519 | **/ |
| 2520 | UINT8 RDEQT; |
| 2521 | |
| 2522 | /** Offset 0x0841 - Read Amplifier Training |
| 2523 | Enables/Disable Read Amplifier Training |
| 2524 | $EN_DIS |
| 2525 | **/ |
| 2526 | UINT8 RDAPT; |
| 2527 | |
| 2528 | /** Offset 0x0842 - Write Timing Centering 2D |
| 2529 | Enables/Disable Write Timing Centering 2D |
| 2530 | $EN_DIS |
| 2531 | **/ |
| 2532 | UINT8 WRTC2D; |
| 2533 | |
| 2534 | /** Offset 0x0843 - Read Timing Centering 2D |
| 2535 | Enables/Disable Read Timing Centering 2D |
| 2536 | $EN_DIS |
| 2537 | **/ |
| 2538 | UINT8 RDTC2D; |
| 2539 | |
| 2540 | /** Offset 0x0844 - Write Voltage Centering 2D |
| 2541 | Enables/Disable Write Voltage Centering 2D |
| 2542 | $EN_DIS |
| 2543 | **/ |
| 2544 | UINT8 WRVC2D; |
| 2545 | |
| 2546 | /** Offset 0x0845 - Read Voltage Centering 2D |
| 2547 | Enables/Disable Read Voltage Centering 2D |
| 2548 | $EN_DIS |
| 2549 | **/ |
| 2550 | UINT8 RDVC2D; |
| 2551 | |
| 2552 | /** Offset 0x0846 - Command Voltage Centering |
| 2553 | Enables/Disable Command Voltage Centering |
| 2554 | $EN_DIS |
| 2555 | **/ |
| 2556 | UINT8 CMDVC; |
| 2557 | |
| 2558 | /** Offset 0x0847 - Late Command Training |
| 2559 | Enables/Disable Late Command Training |
| 2560 | $EN_DIS |
| 2561 | **/ |
| 2562 | UINT8 LCT; |
| 2563 | |
| 2564 | /** Offset 0x0848 - Round Trip Latency Training |
| 2565 | Enables/Disable Round Trip Latency Training |
| 2566 | $EN_DIS |
| 2567 | **/ |
| 2568 | UINT8 RTL; |
| 2569 | |
| 2570 | /** Offset 0x0849 - Turn Around Timing Training |
| 2571 | Enables/Disable Turn Around Timing Training |
| 2572 | $EN_DIS |
| 2573 | **/ |
| 2574 | UINT8 TAT; |
| 2575 | |
| 2576 | /** Offset 0x084A - Memory Test |
| 2577 | Enables/Disable Memory Test |
| 2578 | $EN_DIS |
| 2579 | **/ |
| 2580 | UINT8 MEMTST; |
| 2581 | |
| 2582 | /** Offset 0x084B - DIMM SPD Alias Test |
| 2583 | Enables/Disable DIMM SPD Alias Test |
| 2584 | $EN_DIS |
| 2585 | **/ |
| 2586 | UINT8 ALIASCHK; |
| 2587 | |
| 2588 | /** Offset 0x084C - Receive Enable Centering 1D |
| 2589 | Enables/Disable Receive Enable Centering 1D |
| 2590 | $EN_DIS |
| 2591 | **/ |
| 2592 | UINT8 RCVENC1D; |
| 2593 | |
| 2594 | /** Offset 0x084D - Retrain Margin Check |
| 2595 | Enables/Disable Retrain Margin Check |
| 2596 | $EN_DIS |
| 2597 | **/ |
| 2598 | UINT8 RMC; |
| 2599 | |
| 2600 | /** Offset 0x084E - Write Drive Strength Up/Dn independently |
| 2601 | Enables/Disable Write Drive Strength Up/Dn independently |
| 2602 | $EN_DIS |
| 2603 | **/ |
| 2604 | UINT8 WRDSUDT; |
| 2605 | |
| 2606 | /** Offset 0x084F - ECC Support |
| 2607 | Enables/Disable ECC Support |
| 2608 | $EN_DIS |
| 2609 | **/ |
| 2610 | UINT8 EccSupport; |
| 2611 | |
| 2612 | /** Offset 0x0850 - Memory Remap |
| 2613 | Enables/Disable Memory Remap |
| 2614 | $EN_DIS |
| 2615 | **/ |
| 2616 | UINT8 RemapEnable; |
| 2617 | |
| 2618 | /** Offset 0x0851 - Rank Interleave support |
| 2619 | Enables/Disable Rank Interleave support. NOTE: RI and HORI can not be enabled at |
| 2620 | the same time. |
| 2621 | $EN_DIS |
| 2622 | **/ |
| 2623 | UINT8 RankInterleave; |
| 2624 | |
| 2625 | /** Offset 0x0852 - Enhanced Interleave support |
| 2626 | Enables/Disable Enhanced Interleave support |
| 2627 | $EN_DIS |
| 2628 | **/ |
| 2629 | UINT8 EnhancedInterleave; |
| 2630 | |
| 2631 | /** Offset 0x0853 - Ch Hash Support |
| 2632 | Enable/Disable Channel Hash Support. NOTE: ONLY if Memory interleaved Mode |
| 2633 | $EN_DIS |
| 2634 | **/ |
| 2635 | UINT8 ChHashEnable; |
| 2636 | |
| 2637 | /** Offset 0x0854 - Reserved |
| 2638 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2639 | UINT8 Reserved93; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2640 | |
| 2641 | /** Offset 0x0855 - Extern Therm Status |
| 2642 | Enables/Disable Extern Therm Status |
| 2643 | $EN_DIS |
| 2644 | **/ |
| 2645 | UINT8 EnableExtts; |
| 2646 | |
| 2647 | /** Offset 0x0856 - DDR PowerDown and idle counter |
| 2648 | Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) |
| 2649 | $EN_DIS |
| 2650 | **/ |
| 2651 | UINT8 EnablePwrDn; |
| 2652 | |
| 2653 | /** Offset 0x0857 - DDR PowerDown and idle counter |
| 2654 | Enables/Disable DDR PowerDown and idle counter(For LPDDR Only) |
| 2655 | $EN_DIS |
| 2656 | **/ |
| 2657 | UINT8 EnablePwrDnLpddr; |
| 2658 | |
| 2659 | /** Offset 0x0858 - SelfRefresh Enable |
| 2660 | Enables/Disable SelfRefresh Enable |
| 2661 | $EN_DIS |
| 2662 | **/ |
| 2663 | UINT8 SrefCfgEna; |
| 2664 | |
| 2665 | /** Offset 0x0859 - Throttler CKEMin Defeature |
| 2666 | Enables/Disable Throttler CKEMin Defeature(For LPDDR Only) |
| 2667 | $EN_DIS |
| 2668 | **/ |
| 2669 | UINT8 ThrtCkeMinDefeatLpddr; |
| 2670 | |
| 2671 | /** Offset 0x085A - Throttler CKEMin Defeature |
| 2672 | Enables/Disable Throttler CKEMin Defeature |
| 2673 | $EN_DIS |
| 2674 | **/ |
| 2675 | UINT8 ThrtCkeMinDefeat; |
| 2676 | |
| 2677 | /** Offset 0x085B - Reserved |
| 2678 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2679 | UINT8 Reserved94; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2680 | |
| 2681 | /** Offset 0x085C - Exit On Failure (MRC) |
| 2682 | Enables/Disable Exit On Failure (MRC) |
| 2683 | $EN_DIS |
| 2684 | **/ |
| 2685 | UINT8 ExitOnFailure; |
| 2686 | |
| 2687 | /** Offset 0x085D - New Features 1 - MRC |
| 2688 | New Feature Enabling 1, <b>0:Disable</b>, 1:Enable |
| 2689 | 0:Disable, 1:Enable |
| 2690 | **/ |
| 2691 | UINT8 NewFeatureEnable1; |
| 2692 | |
| 2693 | /** Offset 0x085E - New Features 2 - MRC |
| 2694 | New Feature Enabling 2, <b>0:Disable</b>, 1:Enable |
| 2695 | 0:Disable, 1:Enable |
| 2696 | **/ |
| 2697 | UINT8 NewFeatureEnable2; |
| 2698 | |
| 2699 | /** Offset 0x085F - Duty Cycle Correction Training |
| 2700 | Enable/Disable Duty Cycle Correction Training |
| 2701 | $EN_DIS |
| 2702 | **/ |
| 2703 | UINT8 DCC; |
| 2704 | |
| 2705 | /** Offset 0x0860 - Read Voltage Centering 1D |
| 2706 | Enable/Disable Read Voltage Centering 1D |
| 2707 | $EN_DIS |
| 2708 | **/ |
| 2709 | UINT8 RDVC1D; |
| 2710 | |
| 2711 | /** Offset 0x0861 - TxDqTCO Comp Training |
| 2712 | Enable/Disable TxDqTCO Comp Training |
| 2713 | $EN_DIS |
| 2714 | **/ |
| 2715 | UINT8 TXTCO; |
| 2716 | |
| 2717 | /** Offset 0x0862 - ClkTCO Comp Training |
| 2718 | Enable/Disable ClkTCO Comp Training |
| 2719 | $EN_DIS |
| 2720 | **/ |
| 2721 | UINT8 CLKTCO; |
| 2722 | |
| 2723 | /** Offset 0x0863 - CMD Slew Rate Training |
| 2724 | Enable/Disable CMD Slew Rate Training |
| 2725 | $EN_DIS |
| 2726 | **/ |
| 2727 | UINT8 CMDSR; |
| 2728 | |
| 2729 | /** Offset 0x0864 - CMD Drive Strength and Tx Equalization |
| 2730 | Enable/Disable CMD Drive Strength and Tx Equalization |
| 2731 | $EN_DIS |
| 2732 | **/ |
| 2733 | UINT8 CMDDSEQ; |
| 2734 | |
| 2735 | /** Offset 0x0865 - DIMM CA ODT Training |
| 2736 | Enable/Disable DIMM CA ODT Training |
| 2737 | $EN_DIS |
| 2738 | **/ |
| 2739 | UINT8 DIMMODTCA; |
| 2740 | |
| 2741 | /** Offset 0x0866 - TxDqsTCO Comp Training |
| 2742 | Enable/Disable TxDqsTCO Comp Training |
| 2743 | $EN_DIS |
| 2744 | **/ |
| 2745 | UINT8 TXTCODQS; |
| 2746 | |
| 2747 | /** Offset 0x0867 - CMD/CTL Drive Strength Up/Dn 2D |
| 2748 | Enable/Disable CMD/CTL Drive Strength Up/Dn 2D |
| 2749 | $EN_DIS |
| 2750 | **/ |
| 2751 | UINT8 CMDDRUD; |
| 2752 | |
| 2753 | /** Offset 0x0868 - VccDLL Bypass Training |
| 2754 | Enable/Disable VccDLL Bypass Training |
| 2755 | $EN_DIS |
| 2756 | **/ |
| 2757 | UINT8 VCCDLLBP; |
| 2758 | |
| 2759 | /** Offset 0x0869 - PanicVttDnLp Training |
| 2760 | Enable/Disable PanicVttDnLp Training |
| 2761 | $EN_DIS |
| 2762 | **/ |
| 2763 | UINT8 PVTTDNLP; |
| 2764 | |
| 2765 | /** Offset 0x086A - Read Vref Decap Training* |
| 2766 | Enable/Disable Read Vref Decap Training* |
| 2767 | $EN_DIS |
| 2768 | **/ |
| 2769 | UINT8 RDVREFDC; |
| 2770 | |
| 2771 | /** Offset 0x086B - Vddq Training |
| 2772 | Enable/Disable Vddq Training |
| 2773 | $EN_DIS |
| 2774 | **/ |
| 2775 | UINT8 VDDQT; |
| 2776 | |
| 2777 | /** Offset 0x086C - Rank Margin Tool Per Bit |
| 2778 | Enable/Disable Rank Margin Tool Per Bit |
| 2779 | $EN_DIS |
| 2780 | **/ |
| 2781 | UINT8 RMTBIT; |
| 2782 | |
| 2783 | /** Offset 0x086D - Reserved |
| 2784 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2785 | UINT8 Reserved95; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 2786 | |
| 2787 | /** Offset 0x086E - Reserved |
| 2788 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2789 | UINT8 Reserved96; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2790 | |
| 2791 | /** Offset 0x086F - Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP |
| 2792 | Select if CLK0 is shared between Rank0 and Rank1 in DDR4 DDP |
| 2793 | $EN_DIS |
| 2794 | **/ |
| 2795 | UINT8 Ddr4DdpSharedClock; |
| 2796 | |
| 2797 | /** Offset 0x0870 - Select if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP |
| 2798 | ESelect if ZQ pin is shared between Rank0 and Rank1 in DDR4 DDP |
| 2799 | $EN_DIS |
| 2800 | **/ |
| 2801 | UINT8 Ddr4DdpSharedZq; |
| 2802 | |
| 2803 | /** Offset 0x0871 - Ch Hash Interleaved Bit |
| 2804 | Select the BIT to be used for Channel Interleaved mode. NOTE: BIT7 will interlave |
| 2805 | the channels at a 2 cacheline granularity, BIT8 at 4 and BIT9 at 8. Default is BIT8 |
| 2806 | 0:BIT6, 1:BIT7, 2:BIT8, 3:BIT9, 4:BIT10, 5:BIT11, 6:BIT12, 7:BIT13 |
| 2807 | **/ |
| 2808 | UINT8 ChHashInterleaveBit; |
| 2809 | |
| 2810 | /** Offset 0x0872 - Ch Hash Mask |
| 2811 | Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to |
| 2812 | BITS [19:6] Default is 0x30CC |
| 2813 | **/ |
| 2814 | UINT16 ChHashMask; |
| 2815 | |
| 2816 | /** Offset 0x0874 - Base reference clock value |
| 2817 | Base reference clock value, in Hertz(Default is 100Hz) |
| 2818 | 100000000:100Hz, 125000000:125Hz, 167000000:167Hz, 250000000:250Hz |
| 2819 | **/ |
| 2820 | UINT32 BClkFrequency; |
| 2821 | |
| 2822 | /** Offset 0x0878 - EPG DIMM Idd3N |
| 2823 | Active standby current (Idd3N) in milliamps from datasheet. Must be calculated on |
| 2824 | a per DIMM basis. Default is 26 |
| 2825 | **/ |
| 2826 | UINT16 Idd3n; |
| 2827 | |
| 2828 | /** Offset 0x087A - EPG DIMM Idd3P |
| 2829 | Active power-down current (Idd3P) in milliamps from datasheet. Must be calculated |
| 2830 | on a per DIMM basis. Default is 11 |
| 2831 | **/ |
| 2832 | UINT16 Idd3p; |
| 2833 | |
| 2834 | /** Offset 0x087C - CMD Normalization |
| 2835 | Enable/Disable CMD Normalization |
| 2836 | $EN_DIS |
| 2837 | **/ |
| 2838 | UINT8 CMDNORM; |
| 2839 | |
| 2840 | /** Offset 0x087D - Early DQ Write Drive Strength and Equalization Training |
| 2841 | Enable/Disable Early DQ Write Drive Strength and Equalization Training |
| 2842 | $EN_DIS |
| 2843 | **/ |
| 2844 | UINT8 EWRDSEQ; |
| 2845 | |
| 2846 | /** Offset 0x087E - Reserved |
| 2847 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 2848 | UINT8 Reserved97; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 2849 | |
| 2850 | /** Offset 0x087F - Idle Energy Mc0Ch0Dimm0 |
| 2851 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2852 | **/ |
| 2853 | UINT8 IdleEnergyMc0Ch0Dimm0; |
| 2854 | |
| 2855 | /** Offset 0x0880 - Idle Energy Mc0Ch0Dimm1 |
| 2856 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2857 | **/ |
| 2858 | UINT8 IdleEnergyMc0Ch0Dimm1; |
| 2859 | |
| 2860 | /** Offset 0x0881 - Idle Energy Mc0Ch1Dimm0 |
| 2861 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2862 | **/ |
| 2863 | UINT8 IdleEnergyMc0Ch1Dimm0; |
| 2864 | |
| 2865 | /** Offset 0x0882 - Idle Energy Mc0Ch1Dimm1 |
| 2866 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2867 | **/ |
| 2868 | UINT8 IdleEnergyMc0Ch1Dimm1; |
| 2869 | |
| 2870 | /** Offset 0x0883 - Idle Energy Mc1Ch0Dimm0 |
| 2871 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2872 | **/ |
| 2873 | UINT8 IdleEnergyMc1Ch0Dimm0; |
| 2874 | |
| 2875 | /** Offset 0x0884 - Idle Energy Mc1Ch0Dimm1 |
| 2876 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2877 | **/ |
| 2878 | UINT8 IdleEnergyMc1Ch0Dimm1; |
| 2879 | |
| 2880 | /** Offset 0x0885 - Idle Energy Mc1Ch1Dimm0 |
| 2881 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2882 | **/ |
| 2883 | UINT8 IdleEnergyMc1Ch1Dimm0; |
| 2884 | |
| 2885 | /** Offset 0x0886 - Idle Energy Mc1Ch1Dimm1 |
| 2886 | Idle Energy Consumed for 1 clk w/dimm idle/cke on, range[63;0],(10= Def) |
| 2887 | **/ |
| 2888 | UINT8 IdleEnergyMc1Ch1Dimm1; |
| 2889 | |
| 2890 | /** Offset 0x0887 - PowerDown Energy Mc0Ch0Dimm0 |
| 2891 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2892 | **/ |
| 2893 | UINT8 PdEnergyMc0Ch0Dimm0; |
| 2894 | |
| 2895 | /** Offset 0x0888 - PowerDown Energy Mc0Ch0Dimm1 |
| 2896 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2897 | **/ |
| 2898 | UINT8 PdEnergyMc0Ch0Dimm1; |
| 2899 | |
| 2900 | /** Offset 0x0889 - PowerDown Energy Mc0Ch1Dimm0 |
| 2901 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2902 | **/ |
| 2903 | UINT8 PdEnergyMc0Ch1Dimm0; |
| 2904 | |
| 2905 | /** Offset 0x088A - PowerDown Energy Mc0Ch1Dimm1 |
| 2906 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2907 | **/ |
| 2908 | UINT8 PdEnergyMc0Ch1Dimm1; |
| 2909 | |
| 2910 | /** Offset 0x088B - PowerDown Energy Mc1Ch0Dimm0 |
| 2911 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2912 | **/ |
| 2913 | UINT8 PdEnergyMc1Ch0Dimm0; |
| 2914 | |
| 2915 | /** Offset 0x088C - PowerDown Energy Mc1Ch0Dimm1 |
| 2916 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2917 | **/ |
| 2918 | UINT8 PdEnergyMc1Ch0Dimm1; |
| 2919 | |
| 2920 | /** Offset 0x088D - PowerDown Energy Mc1Ch1Dimm0 |
| 2921 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2922 | **/ |
| 2923 | UINT8 PdEnergyMc1Ch1Dimm0; |
| 2924 | |
| 2925 | /** Offset 0x088E - PowerDown Energy Mc1Ch1Dimm1 |
| 2926 | PowerDown Energy Consumed w/dimm idle/cke off, range[63;0],(6= Def) |
| 2927 | **/ |
| 2928 | UINT8 PdEnergyMc1Ch1Dimm1; |
| 2929 | |
| 2930 | /** Offset 0x088F - Activate Energy Mc0Ch0Dimm0 |
| 2931 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2932 | **/ |
| 2933 | UINT8 ActEnergyMc0Ch0Dimm0; |
| 2934 | |
| 2935 | /** Offset 0x0890 - Activate Energy Mc0Ch0Dimm1 |
| 2936 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2937 | **/ |
| 2938 | UINT8 ActEnergyMc0Ch0Dimm1; |
| 2939 | |
| 2940 | /** Offset 0x0891 - Activate Energy Mc0Ch1Dimm0 |
| 2941 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2942 | **/ |
| 2943 | UINT8 ActEnergyMc0Ch1Dimm0; |
| 2944 | |
| 2945 | /** Offset 0x0892 - Activate Energy Mc0Ch1Dimm1 |
| 2946 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2947 | **/ |
| 2948 | UINT8 ActEnergyMc0Ch1Dimm1; |
| 2949 | |
| 2950 | /** Offset 0x0893 - Activate Energy Mc1Ch0Dimm0 |
| 2951 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2952 | **/ |
| 2953 | UINT8 ActEnergyMc1Ch0Dimm0; |
| 2954 | |
| 2955 | /** Offset 0x0894 - Activate Energy Mc1Ch0Dimm1 |
| 2956 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2957 | **/ |
| 2958 | UINT8 ActEnergyMc1Ch0Dimm1; |
| 2959 | |
| 2960 | /** Offset 0x0895 - Activate Energy Mc1Ch1Dimm0 |
| 2961 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2962 | **/ |
| 2963 | UINT8 ActEnergyMc1Ch1Dimm0; |
| 2964 | |
| 2965 | /** Offset 0x0896 - Activate Energy Mc1Ch1Dimm1 |
| 2966 | Activate Energy Contribution, range[255;0],(172= Def) |
| 2967 | **/ |
| 2968 | UINT8 ActEnergyMc1Ch1Dimm1; |
| 2969 | |
| 2970 | /** Offset 0x0897 - Read Energy Mc0Ch0Dimm0 |
| 2971 | Read Energy Contribution, range[255;0],(212= Def) |
| 2972 | **/ |
| 2973 | UINT8 RdEnergyMc0Ch0Dimm0; |
| 2974 | |
| 2975 | /** Offset 0x0898 - Read Energy Mc0Ch0Dimm1 |
| 2976 | Read Energy Contribution, range[255;0],(212= Def) |
| 2977 | **/ |
| 2978 | UINT8 RdEnergyMc0Ch0Dimm1; |
| 2979 | |
| 2980 | /** Offset 0x0899 - Read Energy Mc0Ch1Dimm0 |
| 2981 | Read Energy Contribution, range[255;0],(212= Def) |
| 2982 | **/ |
| 2983 | UINT8 RdEnergyMc0Ch1Dimm0; |
| 2984 | |
| 2985 | /** Offset 0x089A - Read Energy Mc0Ch1Dimm1 |
| 2986 | Read Energy Contribution, range[255;0],(212= Def) |
| 2987 | **/ |
| 2988 | UINT8 RdEnergyMc0Ch1Dimm1; |
| 2989 | |
| 2990 | /** Offset 0x089B - Read Energy Mc1Ch0Dimm0 |
| 2991 | Read Energy Contribution, range[255;0],(212= Def) |
| 2992 | **/ |
| 2993 | UINT8 RdEnergyMc1Ch0Dimm0; |
| 2994 | |
| 2995 | /** Offset 0x089C - Read Energy Mc1Ch0Dimm1 |
| 2996 | Read Energy Contribution, range[255;0],(212= Def) |
| 2997 | **/ |
| 2998 | UINT8 RdEnergyMc1Ch0Dimm1; |
| 2999 | |
| 3000 | /** Offset 0x089D - Read Energy Mc1Ch1Dimm0 |
| 3001 | Read Energy Contribution, range[255;0],(212= Def) |
| 3002 | **/ |
| 3003 | UINT8 RdEnergyMc1Ch1Dimm0; |
| 3004 | |
| 3005 | /** Offset 0x089E - Read Energy Mc1Ch1Dimm1 |
| 3006 | Read Energy Contribution, range[255;0],(212= Def) |
| 3007 | **/ |
| 3008 | UINT8 RdEnergyMc1Ch1Dimm1; |
| 3009 | |
| 3010 | /** Offset 0x089F - Write Energy Mc0Ch0Dimm0 |
| 3011 | Write Energy Contribution, range[255;0],(221= Def) |
| 3012 | **/ |
| 3013 | UINT8 WrEnergyMc0Ch0Dimm0; |
| 3014 | |
| 3015 | /** Offset 0x08A0 - Write Energy Mc0Ch0Dimm1 |
| 3016 | Write Energy Contribution, range[255;0],(221= Def) |
| 3017 | **/ |
| 3018 | UINT8 WrEnergyMc0Ch0Dimm1; |
| 3019 | |
| 3020 | /** Offset 0x08A1 - Write Energy Mc0Ch1Dimm0 |
| 3021 | Write Energy Contribution, range[255;0],(221= Def) |
| 3022 | **/ |
| 3023 | UINT8 WrEnergyMc0Ch1Dimm0; |
| 3024 | |
| 3025 | /** Offset 0x08A2 - Write Energy Mc0Ch1Dimm1 |
| 3026 | Write Energy Contribution, range[255;0],(221= Def) |
| 3027 | **/ |
| 3028 | UINT8 WrEnergyMc0Ch1Dimm1; |
| 3029 | |
| 3030 | /** Offset 0x08A3 - Write Energy Mc1Ch0Dimm0 |
| 3031 | Write Energy Contribution, range[255;0],(221= Def) |
| 3032 | **/ |
| 3033 | UINT8 WrEnergyMc1Ch0Dimm0; |
| 3034 | |
| 3035 | /** Offset 0x08A4 - Write Energy Mc1Ch0Dimm1 |
| 3036 | Write Energy Contribution, range[255;0],(221= Def) |
| 3037 | **/ |
| 3038 | UINT8 WrEnergyMc1Ch0Dimm1; |
| 3039 | |
| 3040 | /** Offset 0x08A5 - Write Energy Mc1Ch1Dimm0 |
| 3041 | Write Energy Contribution, range[255;0],(221= Def) |
| 3042 | **/ |
| 3043 | UINT8 WrEnergyMc1Ch1Dimm0; |
| 3044 | |
| 3045 | /** Offset 0x08A6 - Write Energy Mc1Ch1Dimm1 |
| 3046 | Write Energy Contribution, range[255;0],(221= Def) |
| 3047 | **/ |
| 3048 | UINT8 WrEnergyMc1Ch1Dimm1; |
| 3049 | |
| 3050 | /** Offset 0x08A7 - Throttler CKEMin Timer |
| 3051 | Timer value for CKEMin, range[255;0]. Req'd min of SC_ROUND_T + BYTE_LENGTH (4). |
| 3052 | Dfault is 0x00 |
| 3053 | **/ |
| 3054 | UINT8 ThrtCkeMinTmr; |
| 3055 | |
| 3056 | /** Offset 0x08A8 - Reserved |
| 3057 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3058 | UINT8 Reserved98; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3059 | |
| 3060 | /** Offset 0x08A9 - Reserved |
| 3061 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3062 | UINT8 Reserved99; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3063 | |
| 3064 | /** Offset 0x08AA - Rapl Power Floor Ch0 |
| 3065 | Power budget ,range[255;0],(0= 5.3W Def) |
| 3066 | **/ |
| 3067 | UINT8 RaplPwrFlCh0; |
| 3068 | |
| 3069 | /** Offset 0x08AB - Rapl Power Floor Ch1 |
| 3070 | Power budget ,range[255;0],(0= 5.3W Def) |
| 3071 | **/ |
| 3072 | UINT8 RaplPwrFlCh1; |
| 3073 | |
| 3074 | /** Offset 0x08AC - Command Rate Support |
| 3075 | CMD Rate and Limit Support Option. NOTE: ONLY supported in 1N Mode, Default is 3 CMDs |
| 3076 | 0:Disable, 5:2 CMDS, 7:3 CMDS, 9:4 CMDS, 11:5 CMDS, 13:6 CMDS, 15:7 CMDS |
| 3077 | **/ |
| 3078 | UINT8 EnCmdRate; |
| 3079 | |
| 3080 | /** Offset 0x08AD - REFRESH_2X_MODE |
| 3081 | 0- (Default)Disabled 1-iMC enables 2xRef when Warm and Hot 2- iMC enables 2xRef when Hot |
| 3082 | 0:Disable, 1:Enabled for WARM or HOT, 2:Enabled HOT only |
| 3083 | **/ |
| 3084 | UINT8 Refresh2X; |
| 3085 | |
| 3086 | /** Offset 0x08AE - Energy Performance Gain |
| 3087 | Enable/disable(default) Energy Performance Gain. |
| 3088 | $EN_DIS |
| 3089 | **/ |
| 3090 | UINT8 EpgEnable; |
| 3091 | |
| 3092 | /** Offset 0x08AF - Reserved |
| 3093 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3094 | UINT8 Reserved100; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3095 | |
| 3096 | /** Offset 0x08B0 - User Manual Threshold |
| 3097 | Disabled: Predefined threshold will be used.\n |
| 3098 | Enabled: User Input will be used. |
| 3099 | $EN_DIS |
| 3100 | **/ |
| 3101 | UINT8 UserThresholdEnable; |
| 3102 | |
| 3103 | /** Offset 0x08B1 - User Manual Budget |
| 3104 | Disabled: Configuration of memories will defined the Budget value.\n |
| 3105 | Enabled: User Input will be used. |
| 3106 | $EN_DIS |
| 3107 | **/ |
| 3108 | UINT8 UserBudgetEnable; |
| 3109 | |
| 3110 | /** Offset 0x08B2 - Power Down Mode |
| 3111 | This option controls command bus tristating during idle periods |
| 3112 | 0x0:No Power Down, 0x1:APD, 0x6:PPD DLL OFF, 0xFF:Auto |
| 3113 | **/ |
| 3114 | UINT8 PowerDownMode; |
| 3115 | |
| 3116 | /** Offset 0x08B3 - Pwr Down Idle Timer |
| 3117 | The minimum value should = to the worst case Roundtrip delay + Burst_Length. 0 means |
| 3118 | AUTO: 64 for ULX/ULT, 128 for DT/Halo |
| 3119 | **/ |
| 3120 | UINT8 PwdwnIdleCounter; |
| 3121 | |
| 3122 | /** Offset 0x08B4 - Page Close Idle Timeout |
| 3123 | This option controls Page Close Idle Timeout |
| 3124 | 0:Enabled, 1:Disabled |
| 3125 | **/ |
| 3126 | UINT8 DisPgCloseIdleTimeout; |
| 3127 | |
| 3128 | /** Offset 0x08B5 - Bitmask of ranks that have CA bus terminated |
| 3129 | Offset 225 LPDDR4: Bitmask of ranks that have CA bus terminated. <b>0x01=Default, |
| 3130 | Rank0 is terminating and Rank1 is non-terminating</b> |
| 3131 | **/ |
| 3132 | UINT8 CmdRanksTerminated; |
| 3133 | |
| 3134 | /** Offset 0x08B6 - PcdSerialDebugLevel |
| 3135 | Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, |
| 3136 | Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, |
| 3137 | Info & Verbose. |
| 3138 | 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load |
| 3139 | Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose |
| 3140 | **/ |
| 3141 | UINT8 PcdSerialDebugLevel; |
| 3142 | |
| 3143 | /** Offset 0x08B7 - Safe Mode Support |
| 3144 | This option configures the varous items in the IO and MC to be more conservative.(def=Disable) |
| 3145 | $EN_DIS |
| 3146 | **/ |
| 3147 | UINT8 SafeMode; |
| 3148 | |
| 3149 | /** Offset 0x08B8 - Ask MRC to clear memory content |
| 3150 | Ask MRC to clear memory content <b>0: Do not Clear Memory;</b> 1: Clear Memory. |
| 3151 | $EN_DIS |
| 3152 | **/ |
| 3153 | UINT8 CleanMemory; |
| 3154 | |
| 3155 | /** Offset 0x08B9 - LpDdrDqDqsReTraining |
| 3156 | Enable/Disable TxDqDqs ReTraining for LP4/5 and DDR5 |
| 3157 | $EN_DIS |
| 3158 | **/ |
| 3159 | UINT8 LpDdrDqDqsReTraining; |
| 3160 | |
| 3161 | /** Offset 0x08BA - TCSS USB Port Enable |
| 3162 | Bitmap for per port enabling |
| 3163 | **/ |
| 3164 | UINT8 UsbTcPortEnPreMem; |
| 3165 | |
| 3166 | /** Offset 0x08BB - Reserved |
| 3167 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3168 | UINT8 Reserved101; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3169 | |
| 3170 | /** Offset 0x08BC - Post Code Output Port |
| 3171 | This option configures Post Code Output Port |
| 3172 | **/ |
| 3173 | UINT16 PostCodeOutputPort; |
| 3174 | |
| 3175 | /** Offset 0x08BE - RMTLoopCount |
| 3176 | Specifies the Loop Count to be used during Rank Margin Tool Testing. 0 - AUTO |
| 3177 | **/ |
| 3178 | UINT8 RMTLoopCount; |
| 3179 | |
| 3180 | /** Offset 0x08BF - Enable/Disable SA CRID |
| 3181 | Enable: SA CRID, Disable (Default): SA CRID |
| 3182 | $EN_DIS |
| 3183 | **/ |
| 3184 | UINT8 CridEnable; |
| 3185 | |
| 3186 | /** Offset 0x08C0 - WRC Feature |
| 3187 | Enable/Disable WRC (Write Cache) feature of IOP. When feature is enabled, supports |
| 3188 | IO devices allocating onto the ring and into LLC. WRC is fused on by default. |
| 3189 | $EN_DIS |
| 3190 | **/ |
| 3191 | UINT8 WrcFeatureEnable; |
| 3192 | |
| 3193 | /** Offset 0x08C1 - Reserved |
| 3194 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3195 | UINT8 Reserved102[3]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3196 | |
| 3197 | /** Offset 0x08C4 - BCLK RFI Frequency |
| 3198 | Bclk RFI Frequency for each SAGV point in Hz units. 98000000Hz = 98MHz <b>0 - No |
| 3199 | RFI Tuning</b>. Range is 98Mhz-100Mhz. |
| 3200 | **/ |
| 3201 | UINT32 BclkRfiFreq[4]; |
| 3202 | |
| 3203 | /** Offset 0x08D4 - Size of PCIe IMR. |
| 3204 | Size of PCIe IMR in megabytes |
| 3205 | **/ |
| 3206 | UINT16 PcieImrSize; |
| 3207 | |
| 3208 | /** Offset 0x08D6 - Enable PCIe IMR |
| 3209 | 0: Disable(AUTO), 1: Enable |
| 3210 | $EN_DIS |
| 3211 | **/ |
| 3212 | UINT8 PcieImrEnabled; |
| 3213 | |
| 3214 | /** Offset 0x08D7 - Enable PCIe IMR |
| 3215 | 1: PCH PCIE, 2: SA PCIE. If PCIeImrEnabled is TRUE then this will use to select |
| 3216 | the Root port location from PCH PCIe or SA PCIe |
| 3217 | $EN_DIS |
| 3218 | **/ |
| 3219 | UINT8 PcieImrRpLocation; |
| 3220 | |
| 3221 | /** Offset 0x08D8 - Root port number for IMR. |
| 3222 | Root port number for IMR.If PCieImrRpLocation is PCH PCIe then select root port |
| 3223 | from 0 to 23 and if it is SA PCIe then select root port from 0 to 3 |
| 3224 | **/ |
| 3225 | UINT8 PcieImrRpSelection; |
| 3226 | |
| 3227 | /** Offset 0x08D9 - SerialDebugMrcLevel |
| 3228 | MRC Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, |
| 3229 | Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, |
| 3230 | Info & Verbose. |
| 3231 | 0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warnings and Info, 4:Load |
| 3232 | Error Warnings and Info & Event, 5:Load Error Warnings Info and Verbose |
| 3233 | **/ |
| 3234 | UINT8 SerialDebugMrcLevel; |
| 3235 | |
| 3236 | /** Offset 0x08DA - Ddr4OneDpc |
| 3237 | DDR4 1DPC performance feature for 2R DIMMs. Can be enabled on DIMM0 or DIMM1 only, |
| 3238 | or on both (default) |
| 3239 | 0: Disabled, 1: Enabled on DIMM0 only, 2: Enabled on DIMM1 only, 3: Enabled |
| 3240 | **/ |
| 3241 | UINT8 Ddr4OneDpc; |
| 3242 | |
| 3243 | /** Offset 0x08DB - Reserved |
| 3244 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3245 | UINT8 Reserved103; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3246 | |
| 3247 | /** Offset 0x08DC - Reserved |
| 3248 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3249 | UINT8 Reserved104; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3250 | |
| 3251 | /** Offset 0x08DD - Reserved |
| 3252 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3253 | UINT8 Reserved105; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3254 | |
| 3255 | /** Offset 0x08DE - REFRESH_PANIC_WM |
| 3256 | DEPRECATED |
| 3257 | **/ |
| 3258 | UINT8 RefreshPanicWm; |
| 3259 | |
| 3260 | /** Offset 0x08DF - REFRESH_HP_WM |
| 3261 | DEPRECATED |
| 3262 | **/ |
| 3263 | UINT8 RefreshHpWm; |
| 3264 | |
| 3265 | /** Offset 0x08E0 - Command Pins Mapping |
| 3266 | BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller |
| 3267 | 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. |
| 3268 | **/ |
| 3269 | UINT8 Lp5CccConfig; |
| 3270 | |
| 3271 | /** Offset 0x08E1 - Command Pins Mirrored |
| 3272 | BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller |
| 3273 | 1 Channel [3:0]. 0 = No Command Mirror and 1 = Command Mirror. |
| 3274 | **/ |
| 3275 | UINT8 CmdMirror; |
| 3276 | |
| 3277 | /** Offset 0x08E2 - Reserved |
| 3278 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3279 | UINT8 Reserved106; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3280 | |
| 3281 | /** Offset 0x08E3 - Reserved |
| 3282 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3283 | UINT8 Reserved107; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3284 | |
| 3285 | /** Offset 0x08E4 - Reserved |
| 3286 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3287 | UINT8 Reserved108; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3288 | |
| 3289 | /** Offset 0x08E5 - Reserved |
| 3290 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3291 | UINT8 Reserved109; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3292 | |
| 3293 | /** Offset 0x08E6 - Reserved |
| 3294 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3295 | UINT8 Reserved110; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3296 | |
| 3297 | /** Offset 0x08E7 - Reserved |
| 3298 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3299 | UINT8 Reserved111; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3300 | |
| 3301 | /** Offset 0x08E8 - Reserved |
| 3302 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3303 | UINT8 Reserved112; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3304 | |
| 3305 | /** Offset 0x08E9 - Reserved |
| 3306 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3307 | UINT8 Reserved113; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3308 | |
| 3309 | /** Offset 0x08EA - Reserved |
| 3310 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3311 | UINT8 Reserved114; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3312 | |
| 3313 | /** Offset 0x08EB - Skip external display device scanning |
| 3314 | Enable: Do not scan for external display device, Disable (Default): Scan external |
| 3315 | display devices |
| 3316 | $EN_DIS |
| 3317 | **/ |
| 3318 | UINT8 SkipExtGfxScan; |
| 3319 | |
| 3320 | /** Offset 0x08EC - Generate BIOS Data ACPI Table |
| 3321 | Enable: Generate BDAT for MRC RMT or SA PCIe data. Disable (Default): Do not generate it |
| 3322 | $EN_DIS |
| 3323 | **/ |
| 3324 | UINT8 BdatEnable; |
| 3325 | |
| 3326 | /** Offset 0x08ED - Lock PCU Thermal Management registers |
| 3327 | Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 |
| 3328 | $EN_DIS |
| 3329 | **/ |
| 3330 | UINT8 LockPTMregs; |
| 3331 | |
| 3332 | /** Offset 0x08EE - Reserved |
| 3333 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3334 | UINT8 Reserved115; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3335 | |
| 3336 | /** Offset 0x08EF - Panel Power Enable |
| 3337 | Control for enabling/disabling VDD force bit (Required only for early enabling of |
| 3338 | eDP panel). 0=Disable, 1(Default)=Enable |
| 3339 | $EN_DIS |
| 3340 | **/ |
| 3341 | UINT8 PanelPowerEnable; |
| 3342 | |
| 3343 | /** Offset 0x08F0 - BdatTestType |
| 3344 | Indicates the type of Memory Training data to populate into the BDAT ACPI table. |
| 3345 | 0:RMT per Rank, 1:RMT per Bit, 2:Margin2D |
| 3346 | **/ |
| 3347 | UINT8 BdatTestType; |
| 3348 | |
| 3349 | /** Offset 0x08F1 - Reserved |
| 3350 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3351 | UINT8 Reserved116[3]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3352 | |
| 3353 | /** Offset 0x08F4 - PMR Size |
| 3354 | Size of PMR memory buffer. 0x400000 for normal boot and 0x200000 for S3 boot |
| 3355 | **/ |
| 3356 | UINT32 DmaBufferSize; |
| 3357 | |
| 3358 | /** Offset 0x08F8 - VT-d/IOMMU Boot Policy |
| 3359 | BIT0: Enable IOMMU during boot, BIT1: Enable IOMMU when transfer control to OS |
| 3360 | **/ |
| 3361 | UINT8 PreBootDmaMask; |
| 3362 | |
| 3363 | /** Offset 0x08F9 - Reserved |
| 3364 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3365 | UINT8 Reserved117; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3366 | |
| 3367 | /** Offset 0x08FA - Reserved |
| 3368 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3369 | UINT16 Reserved118; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3370 | |
| 3371 | /** Offset 0x08FC - Reserved |
| 3372 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3373 | UINT8 Reserved119; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3374 | |
| 3375 | /** Offset 0x08FD - Reserved |
| 3376 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3377 | UINT8 Reserved120; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3378 | |
| 3379 | /** Offset 0x08FE - Reserved |
| 3380 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3381 | UINT8 Reserved121; |
Selma Bensaid | eb17259 | 2022-09-15 18:37:41 -0700 | [diff] [blame] | 3382 | |
| 3383 | /** Offset 0x08FF - Reserved |
| 3384 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3385 | UINT8 Reserved122[88]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3386 | |
| 3387 | /** Offset 0x0957 - Reserved |
| 3388 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3389 | UINT8 Reserved123; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3390 | |
| 3391 | /** Offset 0x0958 - TotalFlashSize |
| 3392 | Enable/Disable. 0: Disable, define default value of TotalFlashSize , 1: enable |
| 3393 | **/ |
| 3394 | UINT16 TotalFlashSize; |
| 3395 | |
| 3396 | /** Offset 0x095A - BiosSize |
| 3397 | The size of the BIOS region of the IFWI. Used if FspmUpd->FspmConfig.BiosGuard != |
| 3398 | 0. If BiosGuard is enabled, MRC will increase the size of the DPR (DMA Protected |
| 3399 | Range) so that a BIOS Update Script can be stored in the DPR. |
| 3400 | **/ |
| 3401 | UINT16 BiosSize; |
| 3402 | |
| 3403 | /** Offset 0x095C - Reserved |
| 3404 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3405 | UINT8 Reserved124[12]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3406 | |
| 3407 | /** Offset 0x0968 - Smbus dynamic power gating |
| 3408 | Disable or Enable Smbus dynamic power gating. |
| 3409 | $EN_DIS |
| 3410 | **/ |
| 3411 | UINT8 SmbusDynamicPowerGating; |
| 3412 | |
| 3413 | /** Offset 0x0969 - Disable and Lock Watch Dog Register |
| 3414 | Set 1 to clear WDT status, then disable and lock WDT registers. |
| 3415 | $EN_DIS |
| 3416 | **/ |
| 3417 | UINT8 WdtDisableAndLock; |
| 3418 | |
| 3419 | /** Offset 0x096A - SMBUS SPD Write Disable |
| 3420 | Set/Clear Smbus SPD Write Disable. 0: leave SPD Write Disable bit; 1: set SPD Write |
| 3421 | Disable bit. For security recommendations, SPD write disable bit must be set. |
| 3422 | $EN_DIS |
| 3423 | **/ |
| 3424 | UINT8 SmbusSpdWriteDisable; |
| 3425 | |
| 3426 | /** Offset 0x096B - Force ME DID Init Status |
| 3427 | Test, 0: disable, 1: Success, 2: No Memory in Channels, 3: Memory Init Error, Set |
| 3428 | ME DID init stat value |
| 3429 | $EN_DIS |
| 3430 | **/ |
| 3431 | UINT8 DidInitStat; |
| 3432 | |
| 3433 | /** Offset 0x096C - CPU Replaced Polling Disable |
| 3434 | Test, 0: disable, 1: enable, Setting this option disables CPU replacement polling loop |
| 3435 | $EN_DIS |
| 3436 | **/ |
| 3437 | UINT8 DisableCpuReplacedPolling; |
| 3438 | |
| 3439 | /** Offset 0x096D - Check HECI message before send |
| 3440 | Test, 0: disable, 1: enable, Enable/Disable message check. |
| 3441 | $EN_DIS |
| 3442 | **/ |
| 3443 | UINT8 DisableMessageCheck; |
| 3444 | |
| 3445 | /** Offset 0x096E - Skip MBP HOB |
| 3446 | Test, 0: disable, 1: enable, Enable/Disable MOB HOB. |
| 3447 | $EN_DIS |
| 3448 | **/ |
| 3449 | UINT8 SkipMbpHob; |
| 3450 | |
| 3451 | /** Offset 0x096F - HECI2 Interface Communication |
| 3452 | Test, 0: disable, 1: enable, Adds or Removes HECI2 Device from PCI space. |
| 3453 | $EN_DIS |
| 3454 | **/ |
| 3455 | UINT8 HeciCommunication2; |
| 3456 | |
| 3457 | /** Offset 0x0970 - Enable KT device |
| 3458 | Test, 0: disable, 1: enable, Enable or Disable KT device. |
| 3459 | $EN_DIS |
| 3460 | **/ |
| 3461 | UINT8 KtDeviceEnable; |
| 3462 | |
| 3463 | /** Offset 0x0971 - Skip CPU replacement check |
| 3464 | Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check |
| 3465 | $EN_DIS |
| 3466 | **/ |
| 3467 | UINT8 SkipCpuReplacementCheck; |
| 3468 | |
| 3469 | /** Offset 0x0972 - Reserved |
| 3470 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3471 | UINT8 Reserved125[2]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3472 | |
| 3473 | /** Offset 0x0974 - Hybrid Graphics GPIO information for PEG 1 |
| 3474 | Hybrid Graphics GPIO information for PEG 1, for Reset, power and wake GPIOs |
| 3475 | **/ |
| 3476 | UINT32 CpuPcie1Rtd3Gpio[24]; |
| 3477 | |
| 3478 | /** Offset 0x09D4 - Hybrid Graphics GPIO information for PEG 2 |
| 3479 | Hybrid Graphics GPIO information for PEG 2, for Reset, power and wake GPIOs |
| 3480 | **/ |
| 3481 | UINT32 CpuPcie2Rtd3Gpio[24]; |
| 3482 | |
| 3483 | /** Offset 0x0A34 - Hybrid Graphics GPIO information for PEG 3 |
| 3484 | Hybrid Graphics GPIO information for PEG 3, for Reset, power and wake GPIOs |
| 3485 | **/ |
| 3486 | UINT32 CpuPcie3Rtd3Gpio[24]; |
| 3487 | |
| 3488 | /** Offset 0x0A94 - Avx2 Voltage Guardband Scaling Factor |
| 3489 | AVX2 Voltage Guardband Scale factor applied to AVX2 workloads. Range is 0-200 in |
| 3490 | 1/100 units, where a value of 125 would apply a 1.25 scale factor. |
| 3491 | **/ |
| 3492 | UINT8 Avx2VoltageScaleFactor; |
| 3493 | |
| 3494 | /** Offset 0x0A95 - Avx512 Voltage Guardband Scaling Factor |
| 3495 | DEPRECATED |
| 3496 | **/ |
| 3497 | UINT8 Avx512VoltageScaleFactor; |
| 3498 | |
| 3499 | /** Offset 0x0A96 - Serial Io Uart Debug Mode |
| 3500 | Select SerialIo Uart Controller mode |
| 3501 | 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, |
| 3502 | 4:SerialIoUartSkipInit |
| 3503 | **/ |
| 3504 | UINT8 SerialIoUartDebugMode; |
| 3505 | |
| 3506 | /** Offset 0x0A97 - Reserved |
| 3507 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3508 | UINT8 Reserved126; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3509 | |
| 3510 | /** Offset 0x0A98 - SerialIoUartDebugRxPinMux - FSPT |
| 3511 | Select RX pin muxing for SerialIo UART used for debug |
| 3512 | **/ |
| 3513 | UINT32 SerialIoUartDebugRxPinMux; |
| 3514 | |
| 3515 | /** Offset 0x0A9C - SerialIoUartDebugTxPinMux - FSPM |
| 3516 | Select TX pin muxing for SerialIo UART used for debug |
| 3517 | **/ |
| 3518 | UINT32 SerialIoUartDebugTxPinMux; |
| 3519 | |
| 3520 | /** Offset 0x0AA0 - SerialIoUartDebugRtsPinMux - FSPM |
| 3521 | Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS* |
| 3522 | for possible values. |
| 3523 | **/ |
| 3524 | UINT32 SerialIoUartDebugRtsPinMux; |
| 3525 | |
| 3526 | /** Offset 0x0AA4 - SerialIoUartDebugCtsPinMux - FSPM |
| 3527 | Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS* |
| 3528 | for possible values. |
| 3529 | **/ |
| 3530 | UINT32 SerialIoUartDebugCtsPinMux; |
| 3531 | |
| 3532 | /** Offset 0x0AA8 - Reserved |
| 3533 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3534 | UINT8 Reserved127; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3535 | |
| 3536 | /** Offset 0x0AA9 - Reserved |
| 3537 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3538 | UINT8 Reserved128; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3539 | |
| 3540 | /** Offset 0x0AAA - Reserved |
| 3541 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3542 | UINT16 Reserved129; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3543 | |
| 3544 | /** Offset 0x0AAC - Reserved |
| 3545 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3546 | UINT8 Reserved130[4]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3547 | |
| 3548 | /** Offset 0x0AB0 - Reserved |
| 3549 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3550 | UINT8 Reserved131; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3551 | |
| 3552 | /** Offset 0x0AB1 - Reserved |
| 3553 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3554 | UINT8 Reserved132; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3555 | |
| 3556 | /** Offset 0x0AB2 - Reserved |
| 3557 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3558 | UINT8 Reserved133[6]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3559 | |
| 3560 | /** Offset 0x0AB8 - Reserved |
| 3561 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3562 | UINT64 Reserved134; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3563 | |
| 3564 | /** Offset 0x0AC0 - Reserved |
| 3565 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3566 | UINT64 Reserved135; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3567 | |
| 3568 | /** Offset 0x0AC8 - Reserved |
| 3569 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3570 | UINT32 Reserved136; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3571 | |
| 3572 | /** Offset 0x0ACC - Reserved |
| 3573 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3574 | UINT8 Reserved137[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3575 | |
| 3576 | /** Offset 0x0AD4 - Reserved |
| 3577 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3578 | UINT8 Reserved138; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3579 | |
| 3580 | /** Offset 0x0AD5 - Reserved |
| 3581 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3582 | UINT8 Reserved139[3]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3583 | |
| 3584 | /** Offset 0x0AD8 - Reserved |
| 3585 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3586 | UINT32 Reserved140; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3587 | |
| 3588 | /** Offset 0x0ADC - Reserved |
| 3589 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3590 | UINT32 Reserved141; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3591 | |
| 3592 | /** Offset 0x0AE0 - Reserved |
| 3593 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3594 | UINT16 Reserved142; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3595 | |
| 3596 | /** Offset 0x0AE2 - Reserved |
| 3597 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3598 | UINT16 Reserved143; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3599 | |
| 3600 | /** Offset 0x0AE4 - Reserved |
| 3601 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3602 | UINT16 Reserved144; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3603 | |
| 3604 | /** Offset 0x0AE6 - Reserved |
| 3605 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3606 | UINT8 Reserved145; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3607 | |
| 3608 | /** Offset 0x0AE7 - Reserved |
| 3609 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3610 | UINT8 Reserved146; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3611 | |
| 3612 | /** Offset 0x0AE8 - Reserved |
| 3613 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3614 | UINT8 Reserved147; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3615 | |
| 3616 | /** Offset 0x0AE9 - Reserved |
| 3617 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3618 | UINT8 Reserved148; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3619 | |
| 3620 | /** Offset 0x0AEA - Reserved |
| 3621 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3622 | UINT8 Reserved149; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3623 | |
| 3624 | /** Offset 0x0AEB - Reserved |
| 3625 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3626 | UINT8 Reserved150[5]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3627 | |
| 3628 | /** Offset 0x0AF0 - Reserved |
| 3629 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3630 | UINT64 Reserved151; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3631 | |
| 3632 | /** Offset 0x0AF8 - Reserved |
| 3633 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3634 | UINT64 Reserved152; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3635 | |
| 3636 | /** Offset 0x0B00 - Reserved |
| 3637 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3638 | UINT32 Reserved153; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3639 | |
| 3640 | /** Offset 0x0B04 - Reserved |
| 3641 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3642 | UINT16 Reserved154; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3643 | |
| 3644 | /** Offset 0x0B06 - Reserved |
| 3645 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3646 | UINT8 Reserved155; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3647 | |
| 3648 | /** Offset 0x0B07 - Reserved |
| 3649 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3650 | UINT8 Reserved156; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3651 | |
| 3652 | /** Offset 0x0B08 - Reserved |
| 3653 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3654 | UINT8 Reserved157; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3655 | |
| 3656 | /** Offset 0x0B09 - Reserved |
| 3657 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3658 | UINT8 Reserved158; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3659 | |
| 3660 | /** Offset 0x0B0A - Reserved |
| 3661 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3662 | UINT8 Reserved159; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3663 | |
| 3664 | /** Offset 0x0B0B - Reserved |
| 3665 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3666 | UINT8 Reserved160; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3667 | |
| 3668 | /** Offset 0x0B0C - Reserved |
| 3669 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3670 | UINT8 Reserved161; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3671 | |
| 3672 | /** Offset 0x0B0D - Reserved |
| 3673 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3674 | UINT8 Reserved162; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3675 | |
| 3676 | /** Offset 0x0B0E - Reserved |
| 3677 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3678 | UINT16 Reserved163; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3679 | |
| 3680 | /** Offset 0x0B10 - Reserved |
| 3681 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3682 | UINT16 Reserved164; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3683 | |
| 3684 | /** Offset 0x0B12 - Reserved |
| 3685 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3686 | UINT16 Reserved165; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3687 | |
| 3688 | /** Offset 0x0B14 - Reserved |
| 3689 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3690 | UINT16 Reserved166; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3691 | |
| 3692 | /** Offset 0x0B16 - Reserved |
| 3693 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3694 | UINT8 Reserved167[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3695 | |
| 3696 | /** Offset 0x0B1E - Reserved |
| 3697 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3698 | UINT8 Reserved168[8]; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3699 | |
| 3700 | /** Offset 0x0B26 - Reserved |
| 3701 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3702 | UINT16 Reserved169; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3703 | |
| 3704 | /** Offset 0x0B28 - Reserved |
| 3705 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3706 | UINT8 Reserved170; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3707 | |
| 3708 | /** Offset 0x0B29 - Reserved |
| 3709 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3710 | UINT8 Reserved171; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3711 | |
| 3712 | /** Offset 0x0B2A - LP5 Bank Mode |
| 3713 | LP5 Bank Mode. 0: Auto, 1: 8 Bank Mode, 2: 16 Bank Mode, 3: BG Mode, default is 0 |
| 3714 | 0:Auto, 1:8 Bank Mode, 2:16 Bank Mode, 3:BG Mode |
| 3715 | **/ |
| 3716 | UINT8 Lp5BankMode; |
| 3717 | |
| 3718 | /** Offset 0x0B2B - Reserved |
| 3719 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3720 | UINT8 Reserved172; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3721 | |
| 3722 | /** Offset 0x0B2C - Reserved |
| 3723 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3724 | UINT8 Reserved173; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3725 | |
| 3726 | /** Offset 0x0B2D - Reserved |
| 3727 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3728 | UINT8 Reserved174; |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3729 | |
Selma Bensaid | eb17259 | 2022-09-15 18:37:41 -0700 | [diff] [blame] | 3730 | /** Offset 0x0B2E - Reserved |
Bora Guvendik | 9f45f06 | 2022-07-12 17:19:42 -0700 | [diff] [blame] | 3731 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3732 | UINT8 Reserved175; |
Selma Bensaid | eb17259 | 2022-09-15 18:37:41 -0700 | [diff] [blame] | 3733 | |
Selma Bensaid | 67ce1f2 | 2022-10-17 16:29:33 -0700 | [diff] [blame] | 3734 | /** Offset 0x0B2F - Reserved |
Selma Bensaid | eb17259 | 2022-09-15 18:37:41 -0700 | [diff] [blame] | 3735 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3736 | UINT8 Reserved176[5]; |
Selma Bensaid | 67ce1f2 | 2022-10-17 16:29:33 -0700 | [diff] [blame] | 3737 | |
| 3738 | /** Offset 0x0B34 - Reserved |
| 3739 | **/ |
Bora Guvendik | e8d4bac | 2023-01-09 15:57:00 -0800 | [diff] [blame] | 3740 | UINT8 Reserved177[4]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3741 | } FSP_M_CONFIG; |
| 3742 | |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3743 | /** Fsp M UPD Configuration |
| 3744 | **/ |
| 3745 | typedef struct { |
| 3746 | |
| 3747 | /** Offset 0x0000 |
| 3748 | **/ |
| 3749 | FSP_UPD_HEADER FspUpdHeader; |
| 3750 | |
| 3751 | /** Offset 0x0020 |
| 3752 | **/ |
| 3753 | FSPM_ARCH_UPD FspmArchUpd; |
| 3754 | |
| 3755 | /** Offset 0x0040 |
| 3756 | **/ |
| 3757 | FSP_M_CONFIG FspmConfig; |
| 3758 | |
| 3759 | /** Offset 0x0B38 |
| 3760 | **/ |
Bora Guvendik | a6f6e6a | 2022-12-02 12:12:37 -0800 | [diff] [blame] | 3761 | UINT8 Rsvd33[6]; |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3762 | |
Bora Guvendik | 225e79b | 2022-05-31 10:51:17 -0700 | [diff] [blame] | 3763 | /** Offset 0x0B3E |
Bora Guvendik | 42d3cc7 | 2022-05-19 11:49:26 -0700 | [diff] [blame] | 3764 | **/ |
| 3765 | UINT16 UpdTerminator; |
| 3766 | } FSPM_UPD; |
| 3767 | |
| 3768 | #pragma pack() |
| 3769 | |
| 3770 | #endif |