Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 1 | #ifndef CPU_X86_MTRR_H |
| 2 | #define CPU_X86_MTRR_H |
| 3 | |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Nico Huber | ca74f8f | 2018-06-01 21:57:54 +0200 | [diff] [blame] | 5 | #ifndef __ASSEMBLER__ |
| 6 | #include <cpu/x86/msr.h> |
| 7 | #include <arch/cpu.h> |
| 8 | #endif |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 9 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 10 | /* These are the region types */ |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 11 | #define MTRR_TYPE_UNCACHEABLE 0 |
| 12 | #define MTRR_TYPE_WRCOMB 1 |
| 13 | #define MTRR_TYPE_WRTHROUGH 4 |
| 14 | #define MTRR_TYPE_WRPROT 5 |
| 15 | #define MTRR_TYPE_WRBACK 6 |
| 16 | #define MTRR_NUM_TYPES 7 |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 17 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 18 | #define MTRR_CAP_MSR 0x0fe |
Lee Leahy | bfdf248 | 2015-06-18 10:55:19 -0700 | [diff] [blame] | 19 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 20 | #define MTRR_CAP_SMRR (1 << 11) |
| 21 | #define MTRR_CAP_WC (1 << 10) |
| 22 | #define MTRR_CAP_FIX (1 << 8) |
| 23 | #define MTRR_CAP_VCNT 0xff |
Lee Leahy | bfdf248 | 2015-06-18 10:55:19 -0700 | [diff] [blame] | 24 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 25 | #define MTRR_DEF_TYPE_MSR 0x2ff |
| 26 | #define MTRR_DEF_TYPE_MASK 0xff |
| 27 | #define MTRR_DEF_TYPE_EN (1 << 11) |
| 28 | #define MTRR_DEF_TYPE_FIX_EN (1 << 10) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 29 | |
Uwe Hermann | 66d1687 | 2010-10-01 07:27:51 +0000 | [diff] [blame] | 30 | |
Arthur Heymans | e750b38e | 2018-07-20 23:31:59 +0200 | [diff] [blame] | 31 | #define IA32_SMRR_PHYS_BASE 0x1f2 |
| 32 | #define IA32_SMRR_PHYS_MASK 0x1f3 |
Duncan Laurie | 7b67892 | 2012-01-09 22:05:18 -0800 | [diff] [blame] | 33 | |
Arthur Heymans | 06f818c | 2018-07-20 23:41:54 +0200 | [diff] [blame] | 34 | /* Specific to model_6fx and model_1067x */ |
| 35 | #define MSR_SMRR_PHYS_BASE 0xa0 |
| 36 | #define MSR_SMRR_PHYS_MASK 0xa1 |
| 37 | |
Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 38 | #define MTRR_PHYS_BASE(reg) (0x200 + 2 * (reg)) |
| 39 | #define MTRR_PHYS_MASK(reg) (MTRR_PHYS_BASE(reg) + 1) |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 40 | #define MTRR_PHYS_MASK_VALID (1 << 11) |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 41 | |
Lee Leahy | 84d20d0 | 2017-03-07 15:00:18 -0800 | [diff] [blame] | 42 | #define NUM_FIXED_RANGES 88 |
| 43 | #define RANGES_PER_FIXED_MTRR 8 |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 44 | #define MTRR_FIX_64K_00000 0x250 |
| 45 | #define MTRR_FIX_16K_80000 0x258 |
| 46 | #define MTRR_FIX_16K_A0000 0x259 |
| 47 | #define MTRR_FIX_4K_C0000 0x268 |
| 48 | #define MTRR_FIX_4K_C8000 0x269 |
| 49 | #define MTRR_FIX_4K_D0000 0x26a |
| 50 | #define MTRR_FIX_4K_D8000 0x26b |
| 51 | #define MTRR_FIX_4K_E0000 0x26c |
| 52 | #define MTRR_FIX_4K_E8000 0x26d |
| 53 | #define MTRR_FIX_4K_F0000 0x26e |
| 54 | #define MTRR_FIX_4K_F8000 0x26f |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 55 | |
Aaron Durbin | ea0497c | 2017-06-08 10:51:33 -0500 | [diff] [blame] | 56 | #if !defined(__ASSEMBLER__) && !defined(__ROMCC__) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 57 | |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 58 | #include <stdint.h> |
| 59 | #include <stddef.h> |
| 60 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 61 | /* |
| 62 | * The MTRR code has some side effects that the callers should be aware for. |
| 63 | * 1. The call sequence matters. x86_setup_mtrrs() calls |
| 64 | * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent |
| 65 | * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers |
| 66 | * want to call the components of x86_setup_mtrrs() because of other |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame] | 67 | * requirements the ordering should still preserved. |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 68 | * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because |
| 69 | * of the nature of the global MTRR enable flag. Therefore, all direct |
| 70 | * or indirect callers of enable_fixed_mtrr() should ensure that the |
| 71 | * variable MTRR MSRs do not contain bad ranges. |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 72 | * |
| 73 | * Note that this function sets up MTRRs for addresses above 4GiB. |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 74 | */ |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 75 | void x86_setup_mtrrs(void); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 76 | /* |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 77 | * x86_setup_mtrrs_with_detect() does the same thing as x86_setup_mtrrs(), but |
| 78 | * it always dynamically detects the number of variable MTRRs available. |
| 79 | */ |
| 80 | void x86_setup_mtrrs_with_detect(void); |
| 81 | /* |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 82 | * x86_setup_var_mtrrs() parameters: |
| 83 | * address_bits - number of physical address bits supported by cpu |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 84 | * above4gb - if set setup MTRRs for addresses above 4GiB else ignore |
| 85 | * memory ranges above 4GiB |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 86 | */ |
| 87 | void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); |
| 88 | void enable_fixed_mtrr(void); |
Marshall Dawson | c0dbeda | 2017-10-19 09:45:16 -0600 | [diff] [blame] | 89 | /* Unhide Rd/WrDram bits and allow modification for AMD. */ |
| 90 | void fixed_mtrrs_expose_amd_rwdram(void); |
| 91 | /* Hide Rd/WrDram bits and allow modification for AMD. */ |
| 92 | void fixed_mtrrs_hide_amd_rwdram(void); |
Maciej Pijanka | ea92185 | 2009-10-27 14:29:29 +0000 | [diff] [blame] | 93 | void x86_setup_fixed_mtrrs(void); |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 94 | /* Set up fixed MTRRs but do not enable them. */ |
| 95 | void x86_setup_fixed_mtrrs_no_enable(void); |
Kyösti Mälkki | 38a8fb0 | 2014-06-30 13:48:18 +0300 | [diff] [blame] | 96 | void x86_mtrr_check(void); |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 97 | |
| 98 | /* Insert a temporary MTRR range for the duration of coreboot's runtime. |
| 99 | * This function needs to be called after the first MTRR solution is derived. */ |
| 100 | void mtrr_use_temp_range(uintptr_t begin, size_t size, int type); |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 101 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 102 | static inline int get_var_mtrr_count(void) |
| 103 | { |
| 104 | return rdmsr(MTRR_CAP_MSR).lo & MTRR_CAP_VCNT; |
| 105 | } |
| 106 | |
Lee Leahy | 0ca2a06 | 2017-03-06 18:01:04 -0800 | [diff] [blame] | 107 | void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, |
| 108 | unsigned int type); |
Furquan Shaikh | 331ac1b | 2016-03-16 16:12:06 -0700 | [diff] [blame] | 109 | int get_free_var_mtrr(void); |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 110 | |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 111 | asmlinkage void display_mtrrs(void); |
| 112 | |
Nico Huber | ca74f8f | 2018-06-01 21:57:54 +0200 | [diff] [blame] | 113 | /* |
| 114 | * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. |
| 115 | * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. |
| 116 | */ |
| 117 | asmlinkage void *soc_set_mtrrs(void *top_of_stack); |
| 118 | asmlinkage void soc_enable_mtrrs(void); |
| 119 | |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 120 | /* fms: find most significant bit set, stolen from Linux Kernel Source. */ |
| 121 | static inline unsigned int fms(unsigned int x) |
| 122 | { |
| 123 | int r; |
| 124 | |
| 125 | __asm__("bsrl %1,%0\n\t" |
Lee Leahy | 708fc27 | 2017-03-07 12:18:53 -0800 | [diff] [blame] | 126 | "jnz 1f\n\t" |
| 127 | "movl $0,%0\n" |
Aaron Durbin | f4258de | 2017-11-01 15:47:05 -0600 | [diff] [blame] | 128 | "1:" : "=r" (r) : "mr" (x)); |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 129 | return r; |
| 130 | } |
| 131 | |
| 132 | /* fls: find least significant bit set */ |
| 133 | static inline unsigned int fls(unsigned int x) |
| 134 | { |
| 135 | int r; |
| 136 | |
| 137 | __asm__("bsfl %1,%0\n\t" |
Lee Leahy | 708fc27 | 2017-03-07 12:18:53 -0800 | [diff] [blame] | 138 | "jnz 1f\n\t" |
| 139 | "movl $32,%0\n" |
Aaron Durbin | f4258de | 2017-11-01 15:47:05 -0600 | [diff] [blame] | 140 | "1:" : "=r" (r) : "mr" (x)); |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 141 | return r; |
| 142 | } |
Aaron Durbin | ea0497c | 2017-06-08 10:51:33 -0500 | [diff] [blame] | 143 | #endif /* !defined(__ASSEMBLER__) && !defined(__ROMCC__) */ |
Rizwan Qureshi | 8453c4f | 2016-09-07 20:11:11 +0530 | [diff] [blame] | 144 | |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 145 | /* Align up/down to next power of 2, suitable for ROMCC and assembler |
| 146 | too. Range of result 256kB to 128MB is good enough here. */ |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 147 | #define _POW2_MASK(x) ((x>>1)|(x>>2)|(x>>3)|(x>>4)|(x>>5)| \ |
| 148 | (x>>6)|(x>>7)|(x>>8)|((1<<18)-1)) |
| 149 | #define _ALIGN_UP_POW2(x) ((x + _POW2_MASK(x)) & ~_POW2_MASK(x)) |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 150 | #define _ALIGN_DOWN_POW2(x) ((x) & ~_POW2_MASK(x)) |
| 151 | |
| 152 | /* Calculate `4GiB - x` (e.g. absolute address for offset from 4GiB) */ |
Nico Huber | c9e3357 | 2019-02-08 16:09:57 +0100 | [diff] [blame^] | 153 | #define _FROM_4G_TOP(x) (((1 << 20) - ((x) >> 12)) << 12) |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 154 | |
Elyes HAOUAS | 918535a | 2016-07-28 21:25:21 +0200 | [diff] [blame] | 155 | /* At the end of romstage, low RAM 0..CACHE_TM_RAMTOP may be set |
Kyösti Mälkki | 65cc526 | 2016-06-19 20:38:41 +0300 | [diff] [blame] | 156 | * as write-back cacheable to speed up ramstage decompression. |
| 157 | * Note MTRR boundaries, must be power of two. |
| 158 | */ |
| 159 | #define CACHE_TMP_RAMTOP (16<<20) |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 160 | |
Lee Leahy | d0f26fc | 2017-03-08 10:15:03 -0800 | [diff] [blame] | 161 | #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0) |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 162 | # error "CONFIG_XIP_ROM_SIZE is not a power of 2" |
| 163 | #endif |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 164 | |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 165 | /* For ROM caching, generally, try to use the next power of 2. */ |
| 166 | #define OPTIMAL_CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE) |
| 167 | #define OPTIMAL_CACHE_ROM_BASE _FROM_4G_TOP(OPTIMAL_CACHE_ROM_SIZE) |
| 168 | #if (OPTIMAL_CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || \ |
| 169 | (OPTIMAL_CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE)) |
| 170 | # error "Optimal CACHE_ROM_SIZE can't be derived, _POW2_MASK needs refinement." |
| 171 | #endif |
| 172 | |
| 173 | /* Make sure it doesn't overlap CAR, though. If the gap between |
| 174 | CAR and 4GiB is too small, make it at most the size of this |
| 175 | gap. As we can't align up (might overlap again), align down |
| 176 | to get a power of 2 again, for a single MTRR. */ |
| 177 | #define CAR_END (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) |
| 178 | #if CAR_END > OPTIMAL_CACHE_ROM_BASE |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 179 | # define CAR_CACHE_ROM_SIZE _ALIGN_DOWN_POW2(_FROM_4G_TOP(CAR_END)) |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 180 | #else |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 181 | # define CAR_CACHE_ROM_SIZE OPTIMAL_CACHE_ROM_SIZE |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 182 | #endif |
Nico Huber | 6197b76 | 2018-05-26 20:34:21 +0200 | [diff] [blame] | 183 | #if ((CAR_CACHE_ROM_SIZE & (CAR_CACHE_ROM_SIZE - 1)) != 0) |
| 184 | # error "CAR CACHE_ROM_SIZE is not a power of 2, _POW2_MASK needs refinement." |
| 185 | #endif |
| 186 | |
| 187 | /* Last but not least, most (if not all) chipsets have MMIO |
| 188 | between 0xfe000000 and 0xff000000, so limit to 16MiB. */ |
| 189 | #if CAR_CACHE_ROM_SIZE >= 16 * MiB |
| 190 | # define CACHE_ROM_SIZE (16 * MiB) |
| 191 | #else |
| 192 | # define CACHE_ROM_SIZE CAR_CACHE_ROM_SIZE |
Kyösti Mälkki | 5458b9d | 2012-06-30 11:41:08 +0300 | [diff] [blame] | 193 | #endif |
| 194 | |
Nico Huber | b4953a9 | 2018-05-26 17:47:42 +0200 | [diff] [blame] | 195 | #define CACHE_ROM_BASE _FROM_4G_TOP(CACHE_ROM_SIZE) |
Kyösti Mälkki | 107f72e | 2014-01-06 11:06:26 +0200 | [diff] [blame] | 196 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 197 | #endif /* CPU_X86_MTRR_H */ |