Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 1 | #ifndef CPU_X86_MTRR_H |
| 2 | #define CPU_X86_MTRR_H |
| 3 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 4 | /* These are the region types */ |
| 5 | #define MTRR_TYPE_UNCACHEABLE 0 |
| 6 | #define MTRR_TYPE_WRCOMB 1 |
| 7 | /*#define MTRR_TYPE_ 2*/ |
| 8 | /*#define MTRR_TYPE_ 3*/ |
| 9 | #define MTRR_TYPE_WRTHROUGH 4 |
| 10 | #define MTRR_TYPE_WRPROT 5 |
| 11 | #define MTRR_TYPE_WRBACK 6 |
| 12 | #define MTRR_NUM_TYPES 7 |
| 13 | |
| 14 | #define MTRRcap_MSR 0x0fe |
| 15 | #define MTRRdefType_MSR 0x2ff |
| 16 | |
Uwe Hermann | 66d1687 | 2010-10-01 07:27:51 +0000 | [diff] [blame] | 17 | #define MTRRdefTypeEn (1 << 11) |
| 18 | #define MTRRdefTypeFixEn (1 << 10) |
| 19 | |
Duncan Laurie | 7b67892 | 2012-01-09 22:05:18 -0800 | [diff] [blame] | 20 | #define SMRRphysBase_MSR 0x1f2 |
| 21 | #define SMRRphysMask_MSR 0x1f3 |
| 22 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 23 | #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg)) |
| 24 | #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1) |
| 25 | |
Kevin O'Connor | 5bb9fd6 | 2011-01-19 06:32:35 +0000 | [diff] [blame] | 26 | #define MTRRphysMaskValid (1 << 11) |
| 27 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 28 | #define NUM_FIXED_RANGES 88 |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 29 | #define RANGES_PER_FIXED_MTRR 8 |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 30 | #define MTRRfix64K_00000_MSR 0x250 |
| 31 | #define MTRRfix16K_80000_MSR 0x258 |
| 32 | #define MTRRfix16K_A0000_MSR 0x259 |
| 33 | #define MTRRfix4K_C0000_MSR 0x268 |
| 34 | #define MTRRfix4K_C8000_MSR 0x269 |
| 35 | #define MTRRfix4K_D0000_MSR 0x26a |
| 36 | #define MTRRfix4K_D8000_MSR 0x26b |
| 37 | #define MTRRfix4K_E0000_MSR 0x26c |
| 38 | #define MTRRfix4K_E8000_MSR 0x26d |
| 39 | #define MTRRfix4K_F0000_MSR 0x26e |
| 40 | #define MTRRfix4K_F8000_MSR 0x26f |
| 41 | |
Stefan Reinauer | 61aee5f | 2011-04-10 04:15:23 +0000 | [diff] [blame] | 42 | #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * The MTRR code has some side effects that the callers should be aware for. |
| 46 | * 1. The call sequence matters. x86_setup_mtrrs() calls |
| 47 | * x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent |
| 48 | * of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers |
| 49 | * want to call the components of x86_setup_mtrrs() because of other |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame^] | 50 | * requirements the ordering should still preserved. |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 51 | * 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because |
| 52 | * of the nature of the global MTRR enable flag. Therefore, all direct |
| 53 | * or indirect callers of enable_fixed_mtrr() should ensure that the |
| 54 | * variable MTRR MSRs do not contain bad ranges. |
Aaron Durbin | 77a5b40 | 2013-03-26 12:47:47 -0500 | [diff] [blame] | 55 | * 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling |
| 56 | * the caching of the ROM. However, it is set to uncacheable (UC). It |
Martin Roth | 0cb07e3 | 2013-07-09 21:46:01 -0600 | [diff] [blame^] | 57 | * is the responsibility of the caller to enable it by calling |
Aaron Durbin | 77a5b40 | 2013-03-26 12:47:47 -0500 | [diff] [blame] | 58 | * x86_mtrr_enable_rom_caching(). |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 59 | */ |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 60 | void x86_setup_mtrrs(void); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 61 | /* |
| 62 | * x86_setup_var_mtrrs() parameters: |
| 63 | * address_bits - number of physical address bits supported by cpu |
| 64 | * above4gb - 2 means dynamically detect number of variable MTRRs available. |
| 65 | * non-zero means handle memory ranges above 4GiB. |
| 66 | * 0 means ignore memory ranges above 4GiB |
| 67 | */ |
| 68 | void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb); |
| 69 | void enable_fixed_mtrr(void); |
Maciej Pijanka | ea92185 | 2009-10-27 14:29:29 +0000 | [diff] [blame] | 70 | void x86_setup_fixed_mtrrs(void); |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 71 | /* Set up fixed MTRRs but do not enable them. */ |
| 72 | void x86_setup_fixed_mtrrs_no_enable(void); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 73 | int x86_mtrr_check(void); |
Aaron Durbin | 77a5b40 | 2013-03-26 12:47:47 -0500 | [diff] [blame] | 74 | /* ROM caching can be used after variable MTRRs are set up. Beware that |
| 75 | * enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on |
| 76 | * one's IO hole size and WRCOMB resources. Be sure to check the console |
Aaron Durbin | 6ccb1ab | 2013-04-03 09:57:53 -0500 | [diff] [blame] | 77 | * log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that |
| 78 | * on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the |
| 79 | * rom caching will be disabled if all threads run the MTRR code. Therefore, |
| 80 | * one needs to call x86_mtrr_enable_rom_caching() after all threads of the |
| 81 | * same core have run the MTRR code. */ |
Aaron Durbin | 77a5b40 | 2013-03-26 12:47:47 -0500 | [diff] [blame] | 82 | #if CONFIG_CACHE_ROM |
| 83 | void x86_mtrr_enable_rom_caching(void); |
| 84 | void x86_mtrr_disable_rom_caching(void); |
Aaron Durbin | bc07f5d | 2013-03-26 13:09:39 -0500 | [diff] [blame] | 85 | /* Return the variable range MTRR index of the ROM cache. */ |
| 86 | long x86_mtrr_rom_cache_var_index(void); |
Aaron Durbin | 77a5b40 | 2013-03-26 12:47:47 -0500 | [diff] [blame] | 87 | #else |
| 88 | static inline void x86_mtrr_enable_rom_caching(void) {} |
| 89 | static inline void x86_mtrr_disable_rom_caching(void) {} |
Aaron Durbin | bc07f5d | 2013-03-26 13:09:39 -0500 | [diff] [blame] | 90 | static inline long x86_mtrr_rom_cache_var_index(void) { return -1; } |
Aaron Durbin | 77a5b40 | 2013-03-26 12:47:47 -0500 | [diff] [blame] | 91 | #endif /* CONFIG_CACHE_ROM */ |
| 92 | |
Stefan Reinauer | 35b6bbb | 2010-03-28 21:26:54 +0000 | [diff] [blame] | 93 | #endif |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 94 | |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 95 | #if !defined(CONFIG_RAMTOP) |
| 96 | # error "CONFIG_RAMTOP not defined" |
| 97 | #endif |
| 98 | |
Patrick Georgi | 784544b | 2011-10-31 17:07:52 +0100 | [diff] [blame] | 99 | #if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 100 | # error "CONFIG_XIP_ROM_SIZE is not a power of 2" |
| 101 | #endif |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 102 | |
Kyösti Mälkki | 5458b9d | 2012-06-30 11:41:08 +0300 | [diff] [blame] | 103 | #if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE -1)) != 0) |
| 104 | # error "CONFIG_CACHE_ROM_SIZE is not a power of 2" |
| 105 | #endif |
| 106 | |
| 107 | #define CACHE_ROM_BASE (((1<<20) - (CONFIG_CACHE_ROM_SIZE>>12))<<12) |
| 108 | |
Stefan Reinauer | 1d888a9 | 2011-04-21 20:24:43 +0000 | [diff] [blame] | 109 | #if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0 |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 110 | # error "CONFIG_RAMTOP must be a power of 2" |
| 111 | #endif |
| 112 | |
Eric Biederman | c84c190 | 2004-10-14 20:13:01 +0000 | [diff] [blame] | 113 | #endif /* CPU_X86_MTRR_H */ |